dss_comm.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/div/dss_comm.vhd,v $
--*  $Revision: 1.4.2.3 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:45 $                              *


--*                                                            *
--**************************************************************


library ieee;

use ieee.std_logic_1164.all;





entity dss_comm is
  
  port (
    CLK           : in  std_logic;
    RESET         : in  std_logic;
    SET           : in  std_logic_vector(1 downto 0);
    SET_EN        : in  std_logic_vector(1 downto 0);
    DSS_ABORT_1   : out std_logic;
    DSS_ABORT_2   : out std_logic;
    DSS_WARNING_1 : out std_logic;
    DSS_WARNING_2 : out std_logic
    );

end dss_comm;




architecture dss_comm_arc of dss_comm is

begin  -- dss_comm_arc


  abort_set : process (CLK, RESET)
  begin  -- process ctp_set
    if RESET = '1' then                 -- asynchronous reset (active high)
      DSS_ABORT_1 <= '0';
      DSS_ABORT_2 <= '0';
    elsif CLK'event and CLK = '1' then  -- rising clock edge
      if SET_EN(1) = '1' then
        DSS_ABORT_1 <= SET(1);
        DSS_ABORT_2 <= SET(1);
      end if;
    end if;
  end process abort_set;


  warn_set : process (CLK, RESET)
  begin  -- process ctp_set
    if RESET = '1' then                 -- asynchronous reset (active high)
      DSS_WARNING_1 <= '0';
      DSS_WARNING_2 <= '0';
    elsif CLK'event and CLK = '1' then  -- rising clock edge
      if SET_EN(0) = '1' then
        DSS_WARNING_1 <= SET(0);
        DSS_WARNING_2 <= SET(0);
      end if;
    end if;
  end process warn_set;

end dss_comm_arc;

---

Author: M.Niegl

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