l1a_fifo.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/div/l1a_fifo.vhd,v $
--*  $Revision: 1.4.2.3 $                                         *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:45 $                              *


--*                                                            *
--**************************************************************
--------------------------------------------------------------------------------
--     This file is owned and controlled by Xilinx and must be used           --
--     solely for design, simulation, implementation and creation of          --
--     design files limited to Xilinx devices or technologies. Use            --
--     with non-Xilinx devices or technologies is expressly prohibited        --
--     and immediately terminates your license.                               --
--                                                                            --
--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
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--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
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--     (c) Copyright 1995-2007 Xilinx, Inc.                                   --
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--------------------------------------------------------------------------------
-- You must compile the wrapper file l1a_fifo.vhd when simulating
-- the core, l1a_fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).


library ieee;

use ieee.std_logic_1164.all;
-- synthesis translate_off
library XilinxCoreLib;
-- synthesis translate_on





entity l1a_fifo is
  port (
    clk   : in  std_logic;
    din   : in  std_logic_vector(43 downto 0);
    rd_en : in  std_logic;
    srst  : in  std_logic;
    wr_en : in  std_logic;
    dout  : out std_logic_vector(43 downto 0);
    empty : out std_logic;
    full  : out std_logic
    );
end l1a_fifo;


architecture l1a_fifo_a of l1a_fifo is
-- synthesis translate_off
  component wrapped_l1a_fifo
    port (
      clk   : in  std_logic;
      din   : in  std_logic_vector(43 downto 0);
      rd_en : in  std_logic;
      srst  : in  std_logic;
      wr_en : in  std_logic;
      dout  : out std_logic_vector(43 downto 0);
      empty : out std_logic;
      full  : out std_logic);
  end component;

-- Configuration specification 
  for all : wrapped_l1a_fifo use entity XilinxCoreLib.fifo_generator_v4_2(behavioral)
    generic map(
      c_has_int_clk                  => 0,
      c_rd_freq                       => 1,
      c_wr_response_latency          => 1,
      c_has_srst                     => 1,
      c_has_rd_data_count            => 0,
      c_din_width                     => 44,
      c_has_wr_data_count            => 0,
      c_full_flags_rst_val           => 0,
      c_implementation_type          => 0,
      c_family                       => "virtex4" ,
      c_use_embedded_reg             => 1,
      c_has_wr_rst                   => 0,
      c_wr_freq                      => 1,
      c_use_dout_rst                 => 0,
      c_underflow_low                => 0,
      c_has_meminit_file             => 0,
      c_has_overflow                 => 0,
      c_preload_latency              => 2,
      c_dout_width                   => 44,
      c_rd_depth                     => 32,
      c_default_value                => "BlankString",
      c_mif_file_name                => "BlankString",
      c_has_underflow                => 0,
      c_has_rd_rst                   => 0,
      c_has_almost_full              => 0,
      c_has_rst                      => 0,
      c_data_count_width             => 5,
      c_has_wr_ack                   => 0,
      c_use_ecc                      => 0,
      c_wr_ack_low                   => 0,
      c_common_clock                 => 1,
      c_rd_pntr_width                => 5,
      c_use_fwft_data_count          => 0,
      c_has_almost_empty             => 0,
      c_rd_data_count_width          => 5,
      c_enable_rlocs                 => 0,
      c_wr_pntr_width                => 5,
      c_overflow_low                 => 0,
      c_prog_empty_type              => 0,
      c_optimization_mode            => 0,
      c_wr_data_count_width          => 5,
      c_preload_regs                 => 1,
      c_dout_rst_val                 => "0",
      c_has_data_count               => 0,
      c_prog_full_thresh_negate_val  => 29,
      c_wr_depth                     => 32,
      c_prog_empty_thresh_negate_val => 3,
      c_prog_empty_thresh_assert_val => 2,
      c_has_valid                    => 0,
      c_init_wr_pntr_val             => 0,
      c_prog_full_thresh_assert_val  => 30,
      c_use_fifo16_flags             => 0,
      c_has_backup                   => 0,
      c_valid_low                    => 0,
      c_prim_fifo_type               => "512x72",
      c_count_type                   => 0,
      c_prog_full_type               => 0,
      c_memory_type                  => 1);
-- synthesis translate_on
begin
-- synthesis translate_off
  U0 : wrapped_l1a_fifo
    port map (
      clk   => clk ,
      din   => din ,
      rd_en => rd_en,
      srst  => srst,
      wr_en => wr_en,
      dout  => dout,
      empty => empty,
      full  => full);
-- synthesis translate_on

end l1a_fifo_a;

---

Author: M.Niegl

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