onescompaccu.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/eth/onescompaccu.vhd,v $
--*  $Revision: 2.1.2.3 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:46 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

library unisim;

use unisim.vcomponents.all;




entity onescompaccu is
  port (
    CLK       : in  std_logic;
    RESET     : in  std_logic;
    EN        : in  std_logic;
    Ain       : in  std_logic_vector (15 downto 0);
    CARRY_OUT : out std_logic;
    RES       : out std_logic_vector (15 downto 0)
    );
end onescompaccu;


architecture onescompaccu_arc of onescompaccu is

  signal carry_i  : std_logic                     := '0';
  signal fb       : std_logic_vector(15 downto 0) := (others => '0');
  signal result_i : std_logic_vector(15 downto 0) := (others => '0');


  component onescomplementadder
    port(
      CLK   : in  std_logic;
      RESET : in  std_logic;
      EN    : in  std_logic;
      A     : in  std_logic_vector(15 downto 0);
      B     : in  std_logic_vector(15 downto 0);
      C_IN  : in  std_logic;
      C_OUT : out std_logic;
      Y     : out std_logic_vector(15 downto 0)
      );
  end component;

begin

  fb        <= (others => '0') when RESET = '1' else result_i;
  RES       <= result_i;
  CARRY_OUT <= carry_i;

  adder : onescomplementadder
    port map
    (
      CLK   => CLK ,
      RESET => RESET,
      EN    => EN ,
      A     => Ain ,
      B     => fb ,
      C_IN  => carry_i,
      C_OUT => carry_i,
      Y     => result_i 
      );

end onescompaccu_arc;

---

Author: M.Niegl

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