riocheck.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/rio/riocheck.vhd,v $
--*  $Revision: 1.7.2.5 $                                          *
--*  $Name: dev $                                              *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 19:00:05 $                              *



--*                                                            *
--**************************************************************


library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;
library work;
use work.build_parameters.all;
use work.daq_header.all;


entity riocheck is
  
  port (
    CLK      : in  std_logic;
    RES      : in  std_logic;
    EN       : in  std_logic;
    DATA_IN  : in  std_logic_vector(255 downto 0);
    MASK_N   : in  std_logic_vector(7 downto 0) := (others => '1');
    ERR      : out std_logic;
    ERR_TYPE : out std_logic_vector(7 downto 0)
    );

end riocheck;


architecture riocheck_arc of riocheck is

  signal err0_i, err1_i, err2_i, err3_i, err4_i, err5_i, err6_i, err7_i : integer                      := 0;
  signal err_i                                                          : std_logic_vector(7 downto 0) := (others => '0');
  signal err_bit                                                        : std_logic                    := '0';
  signal err_cnt                                                        : std_logic_vector(8 downto 0) := (others => '0');

begin  -- riocheck_arc

  get_error : process (CLK, RES)
  begin  -- process get_error
    if RES = '1' then                   -- asynchronous reset (active low)
      ERR      <= '0';
      ERR_TYPE <= (others => '0');
      err_i    <= (others => '0');
      err0_i   <= 0;
      err1_i   <= 0;
      err2_i   <= 0;
      err3_i   <= 0;
      err4_i   <= 0;
      err5_i   <= 0;
      err6_i   <= 0;
      err7_i   <= 0;
      err_bit  <= '0';
      err_cnt  <= (others => '0');
    elsif CLK'event and CLK = '1' then  -- rising clock edge
      if EN = '1' then
        if err0_i >= kErr_Cnt then
          err_i(0) <= MASK_N(0);
        else
          err_i(0) <= '0';
        end if;
        err0_i <= cnt_ones(DATA_IN(255 downto 224));
        if err1_i >= kErr_Cnt then
          err_i(1) <= MASK_N(1);
        else
          err_i(1) <= '0';
        end if;
        err1_i <= cnt_ones(DATA_IN(223 downto 192));
        if err2_i >= kErr_Cnt then
          err_i(2) <= MASK_N(2);
        else
          err_i(2) <= '0';
        end if;
        err2_i <= cnt_ones(DATA_IN(191 downto 160));
        if err3_i >= kErr_Cnt then
          err_i(3) <= MASK_N(3);
        else
          err_i(3) <= '0';
        end if;
        err3_i <= cnt_ones(DATA_IN(159 downto 128));
        if err4_i >= kErr_Cnt then
          err_i(4) <= MASK_N(4);
        else
          err_i(4) <= '0';
        end if;
        err4_i <= cnt_ones(DATA_IN(127 downto 96));
        if err5_i >= kErr_Cnt then
          err_i(5) <= MASK_N(5);
        else
          err_i(5) <= '0';
        end if;
        err5_i <= cnt_ones(DATA_IN(95 downto 64));
        if err6_i >= kErr_Cnt then
          err_i(6) <= MASK_N(6);
        else
          err_i(6) <= '0';
        end if;
        err6_i <= cnt_ones(DATA_IN(63 downto 32));
        if err7_i >= kErr_Cnt then
          err_i(7) <= MASK_N(7);
        else
          err_i(7) <= '0';
        end if;
        err7_i <= cnt_ones(DATA_IN(31 downto 0));
      end if;

      err_bit <= err_i(7) or err_i(6) or err_i(5) or err_i(4) or err_i(3) or err_i(2) or err_i(1) or err_i(0);

      if err_bit = '1' then
        err_cnt <= err_cnt + 1;
      else
        err_cnt <= (others => '0');
      end if;

      if err_cnt >= kTime_Cnt then
        ERR      <= '1';
        ERR_TYPE <= err_i;
      end if;
      
    end if;
  end process get_error;
  

end riocheck_arc;

---

Author: M.Niegl

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