bunchcycle.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/rio/bunchcycle.vhd,v $ 
--*  $Revision: 1.6.2.7 $                                      *
--*  $Name: dev $                                              *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:47 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;
library work;
use work.daq_header.all;

library unisim;

use unisim.vcomponents.all;


entity bunchcycle is
  port (
    CLK2X      : in  std_logic;
    CLK        : in  std_logic;
    RESET      : in  std_logic;
    EN         : in  std_logic;
    R1         : in  std_logic_vector (4 downto 0);
    R2         : in  std_logic_vector (4 downto 0);
    R3         : in  std_logic_vector (4 downto 0);
    F1         : in  std_logic_vector (4 downto 0);
    F2         : in  std_logic_vector (4 downto 0);
    F3         : in  std_logic_vector (4 downto 0);
    SR1        : in  std_logic;
    SR2        : in  std_logic;
    SR3        : in  std_logic;
    SF1        : in  std_logic;
    SF2        : in  std_logic;
    SF3        : in  std_logic;
    EDGE_RIS1  : out std_logic_vector (5 downto 0);
    EDGE_RIS2  : out std_logic_vector (5 downto 0);
    EDGE_RIS3  : out std_logic_vector (5 downto 0);
    EDGE_FAL1  : out std_logic_vector (5 downto 0);
    EDGE_FAL2  : out std_logic_vector (5 downto 0);
    EDGE_FAL3  : out std_logic_vector (5 downto 0);
    STATUS_ER1 : out std_logic;
    STATUS_ER2 : out std_logic;
    STATUS_ER3 : out std_logic;
    STATUS_EF1 : out std_logic;
    STATUS_EF2 : out std_logic;
    STATUS_EF3 : out std_logic;
    SUM_R_IN   : in  std_logic_vector (5 downto 0);
    SUM_F_IN   : in  std_logic_vector (5 downto 0);
    SUM_R_OUT  : out std_logic_vector (7 downto 0);
    SUM_F_OUT  : out std_logic_vector (7 downto 0)
    );
end bunchcycle;




architecture bunchcycle_arc of bunchcycle is

--*************************** Signal Declarations *****************************
  signal in_ris1  : std_logic_vector(4 downto 0) := (others => '0');
  signal in_ris2  : std_logic_vector(4 downto 0) := (others => '0');
  signal in_fal1  : std_logic_vector(4 downto 0) := (others => '0');
  signal in_fal2  : std_logic_vector(4 downto 0) := (others => '0');
  signal freg_r11 : std_logic_vector(5 downto 0) := (others => '0');
  signal freg_r21 : std_logic_vector(5 downto 0) := (others => '0');
  signal freg_f11 : std_logic_vector(5 downto 0) := (others => '0');
  signal freg_f21 : std_logic_vector(5 downto 0) := (others => '0');
  signal freg_r12 : std_logic_vector(5 downto 0) := (others => '0');
  signal freg_r22 : std_logic_vector(5 downto 0) := (others => '0');
  signal freg_f12 : std_logic_vector(5 downto 0) := (others => '0');
  signal freg_f22 : std_logic_vector(5 downto 0) := (others => '0');
  signal reg_r1   : std_logic_vector(5 downto 0) := (others => '0');
  signal reg_r2   : std_logic_vector(5 downto 0) := (others => '0');
  signal reg_f1   : std_logic_vector(5 downto 0) := (others => '0');
  signal reg_f2   : std_logic_vector(5 downto 0) := (others => '0');
  signal rsr11    : std_logic                    := '0';
  signal rsr21    : std_logic                    := '0';
  signal rsf11    : std_logic                    := '0';
  signal rsf21    : std_logic                    := '0';
  signal rsr12    : std_logic                    := '0';
  signal rsr22    : std_logic                    := '0';
  signal rsf12    : std_logic                    := '0';
  signal rsf22    : std_logic                    := '0';
  signal fal2     : std_logic                    := '0';
  signal ris2     : std_logic                    := '0';
  signal tog      : std_logic                    := '0';
  signal low      : std_logic                    := '0';

begin

  EDGE_RIS3  <= (others => '0');
  EDGE_FAL3  <= (others => '0');
  STATUS_EF3 <= '0';
  STATUS_ER3 <= '0';

  in_ris1 <= R1 when SR1 = '1' else (others => '0');
  in_ris2 <= R2 when SR2 = '1' else (others => '0');
  in_fal1 <= F1 when SF1 = '1' else (others => '0');
  in_fal2 <= F2 when SF2 = '1' else (others => '0');

  freg_r21(5) <= '1' when (freg_r21(4 downto 0) = "11111") and rsr11 = '0' else '0';
  freg_r11(5) <= '0' when (freg_r11(4 downto 0) = "11111") and rsr21 = '0' else rsr11;
  freg_f21(5) <= '0';
  freg_f11(5) <= rsf11;
  freg_r22(5) <= '0';
  freg_r12(5) <= rsr12;
  freg_f22(5) <= '0';
  freg_f12(5) <= rsf12;


  read_out : process (CLK, RESET)
  begin  -- process read
    if RESET = '1' then                 -- asynchronous reset (active high)
      STATUS_EF1 <= '0';
      STATUS_ER1 <= '0';
      STATUS_EF2 <= '0';
      STATUS_ER2 <= '0';
      EDGE_RIS1  <= (others => '0');
      EDGE_FAL1  <= (others => '0');
      EDGE_RIS2  <= (others => '0');
      EDGE_FAL2  <= (others => '0');
    elsif CLK'event and CLK = '1' then  -- rising clock edge
      if (reg_f1 > reg_f2) and (fal2 = '1') then
        EDGE_FAL2 <= reg_f1;
        EDGE_FAL1 <= reg_f2;
      else
        EDGE_FAL2 <= reg_f2;
        EDGE_FAL1 <= reg_f1;
      end if;
      if (reg_r1 > reg_r2) and (ris2 = '1') then
        EDGE_RIS1 <= reg_r2;
        EDGE_RIS2 <= reg_r1;
      else
        EDGE_RIS1 <= reg_r1;
        EDGE_RIS2 <= reg_r2;
      end if;
      STATUS_EF1 <= rsf11 or rsf21;
      STATUS_ER1 <= rsr11 or rsr21;
      STATUS_EF2 <= fal2;
      STATUS_ER2 <= ris2;
    end if;
  end process read_out;

  fal2 <= (rsf11 and (rsf12 or rsf21)) or (rsf21 and rsf22);
  ris2 <= (rsr11 and (rsr12 or rsr21)) or (rsr21 and rsr22);


  sums : process (CLK2X, RESET)
  begin  -- process sums
    if RESET = '1' then                     -- asynchronous reset (active high)
      SUM_R_OUT <= (others => '0');
      SUM_F_OUT <= (others => '0');
    elsif CLK2X'event and CLK2X = '1' then  -- rising clock edge
      SUM_R_OUT <= ("0000000" & SR1) + ("0000000" & SR2);
      SUM_F_OUT <= ("0000000" & SF1) + ("0000000" & SF2);
    end if;
  end process sums;

  reg_r1 <= freg_r11 when rsr11 = '1' else
            freg_r12 when rsr12 = '1' else
            freg_r21 when rsr21 = '1' else
            freg_r22;
  reg_r2 <= freg_r12 when (rsr12 and rsr11) = '1' else
            freg_r21 when (rsr21 and (rsr11 or rsr12)) = '1' else
            freg_r22;
  reg_f1 <= freg_f11 when rsf11 = '1' else
            freg_f12 when rsf12 = '1' else
            freg_f21 when rsf21 = '1' else
            freg_f22;
  reg_f2 <= freg_f12 when (rsf12 and rsf11) = '1' else
            freg_f21 when (rsf21 and (rsf11 or rsf12)) = '1' else
            freg_f22;


  fill : process (CLK2X, RESET)
  begin  -- process fill
    if RESET = '1' then                     -- asynchronous reset (active high)
      freg_r11(4 downto 0) <= (others => '0');
      freg_r21(4 downto 0) <= (others => '0');
      freg_f11(4 downto 0) <= (others => '0');
      freg_f21(4 downto 0) <= (others => '0');
      freg_r12(4 downto 0) <= (others => '0');
      freg_r22(4 downto 0) <= (others => '0');
      freg_f12(4 downto 0) <= (others => '0');
      freg_f22(4 downto 0) <= (others => '0');
      rsr12                <= '0';
      rsr22                <= '0';
      rsf12                <= '0';
      rsf22                <= '0';
      rsr11                <= '0';
      rsr21                <= '0';
      rsf11                <= '0';
      rsf21                <= '0';
      tog                  <= '0';
    elsif CLK2X'event and CLK2X = '1' then  -- rising clock edge
      if EN = '1' then
        
        tog <= not tog;
        -- first half
        if tog = '1' then
          
          if (in_fal1 = 0) and (SR1 = '1') then
            freg_f11(4 downto 0) <= (others => '1');
            rsf11                <= SF1;
            freg_f12(4 downto 0) <= in_fal1;
            rsf12                <= SF1;
            freg_r11(4 downto 0) <= in_ris1;
            rsr11                <= SR1;
            freg_r12(4 downto 0) <= in_ris2;
            rsr12                <= SR2;
          elsif (in_fal2 = 0) and (SR2 = '1') then
            freg_f11(4 downto 0) <= in_fal1;
            rsf11                <= SF1;
            freg_f12(4 downto 0) <= (others => '1');
            rsf12                <= SF2;
            freg_r11(4 downto 0) <= in_ris1;
            rsr11                <= SR1;
            freg_r12(4 downto 0) <= in_ris2;
            rsr12                <= SR2;
          else
            freg_f11(4 downto 0) <= in_fal1;
            rsf11                <= SF1;
            freg_f12(4 downto 0) <= in_fal2;
            rsf12                <= SF2;
            freg_r11(4 downto 0) <= in_ris1;
            rsr11                <= SR1;
            freg_r12(4 downto 0) <= in_ris2;
            rsr12                <= SR2;
          end if;

          -- second half
        else
          
          if (in_fal1 = 0) and (SR1 = '1') then
            freg_f21(4 downto 0) <= (others => '1');
            rsf21                <= SF1;
            freg_f22(4 downto 0) <= in_fal1;
            rsf22                <= SF1;
            freg_r21(4 downto 0) <= in_ris1;
            rsr21                <= SR1;
            freg_r22(4 downto 0) <= in_ris2;
            rsr22                <= SR2;
          elsif (in_fal2 = 0) and (SR2 = '1') then
            freg_f21(4 downto 0) <= in_fal1;
            rsf21                <= SF1;
            freg_f22(4 downto 0) <= (others => '1');
            rsf22                <= SF2;
            freg_r21(4 downto 0) <= in_ris1;
            rsr21                <= SR1;
            freg_r22(4 downto 0) <= in_ris2;
            rsr22                <= SR2;
          else
            freg_f21(4 downto 0) <= in_fal1;
            rsf21                <= SF1;
            freg_f22(4 downto 0) <= in_fal2;
            rsf22                <= SF2;
            freg_r21(4 downto 0) <= in_ris1;
            rsr21                <= SR1;
            freg_r22(4 downto 0) <= in_ris2;
            rsr22                <= SR2;
          end if;
          
        end if;
        
      else
        tog <= '0';
      end if;
    end if;
  end process fill;

end bunchcycle_arc;

---

Author: M.Niegl

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