00001 --**************************************************************
00002 --* *
00003 --* The source code for the ATLAS BCM "AAA" FPGA is made *
00004 --* available via the GNU General Public License (GPL) *
00005 --* unless otherwise stated below. *
00006 --* *
00007 --* In case of problems/questions/bug reports etc. please *
00008 --* contact michael.niegl@cern.ch *
00009 --* *
00010 --**************************************************************
00011
00012 --**************************************************************
00013 --* *
00014 --* $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr2/ddr2_mem_v4_dq_iob.vhd,v $
00015 --* $Revision: 1.3.2.4 $ *
00016 --* $Name: dev $ *
00017 --* $Author: mniegl $ *
00018 --* $Date: 2008/11/03 18:48:14 $ *
00019
00020
00021 --* *
00022 --**************************************************************
00023 -------------------------------------------------------------------------------
00024 -- Copyright (c) 2005 Xilinx, Inc.
00025 -- This design is confidential and proprietary of Xilinx, All Rights Reserved.
00026 -------------------------------------------------------------------------------
00027 -- ____ ____
00028 -- / /\/ /
00029 -- /___/ \ / Vendor: Xilinx
00030 -- \ \ \/ Version: 1.6
00031 -- \ \ Application : MIG
00032 -- / / Filename: ddr2_mem_v4_dq_iob.vhd
00033 -- /___/ /\ Date Last Modified: Wed Jun 1 2005
00034 -- \ \ / \Date Created: Mon May 2 2005
00035 -- \___\/\___\
00036 --
00037 -- Device: Virtex-4
00038 -- Design Name: DDR2_V4
00039 -- Description :
00040 -------------------------------------------------------------------------------
00041
00042
00043 library ieee;
00044
00045 use ieee.std_logic_1164.all;
00046
00047 use ieee.std_logic_unsigned.all;
00048
00049 use ieee.numeric_std.all;
00050
00051 library unisim;
00052
00053 use unisim.vcomponents.all;
00054
00055
00056
00057 entity ddr2_mem_v4_dq_iob is
00058 port (
00059 CLK : in ;
00060 CLK90 : in ;
00061 CAL_CLK : in ;
00062 RESET : in ;
00063 DATA_DLYINC : in ;
00064 DATA_DLYCE : in ;
00065 DATA_DLYRST : in ;
00066 WRITE_DATA_RISE : in ;
00067 WRITE_DATA_FALL : in ;
00068 CTRL_WREN : in ;
00069 DDR_DQ : inout ;
00070 READ_DATA_RISE : out ;
00071 READ_DATA_FALL : out
00072 );
00073
00074 end entity;
00075
00076
00077
00078 architecture arc_v4_dq_iob of ddr2_mem_v4_dq_iob is
00079
00080
00081 component IOBUF
00082 port(
00083 O : out ;
00084 IO : inout ;
00085 I : in ;
00086 T : in
00087 );
00088 end component;
00089
00090
00091 component FDCE
00092 port(
00093 D : in ;
00094 CLR : in ;
00095 C : in ;
00096 Q : out ;
00097 CE : in
00098 );
00099 end component;
00100
00101
00102 component IDELAY
00103 generic(
00104 IOBDELAY_TYPE : := "VARIABLE";
00105 IOBDELAY_VALUE : := 0
00106 );
00107 port(
00108 O : out ;
00109 C : in ;
00110 CE : in ;
00111 I : in ;
00112 INC : in ;
00113 RST : in
00114 );
00115 end component;
00116
00117
00118 component IDDR
00119 generic(
00120 DDR_CLK_EDGE : := "SAME_EDGE_PIPELINED";
00121 SRTYPE : := "SYNC"
00122 );
00123 port(
00124 Q1 : out ;
00125 Q2 : out ;
00126 C : in ;
00127 CE : in ;
00128 D : in ;
00129 R : in ;
00130 S : in
00131 );
00132 end component;
00133
00134
00135 component ODDR
00136 generic(
00137 DDR_CLK_EDGE : := "SAME_EDGE";
00138 SRTYPE : := "SYNC"
00139 );
00140 port(
00141 Q : out ;
00142 C : in ;
00143 CE : in ;
00144 D1 : in ;
00145 D2 : in ;
00146 R : in ;
00147 S : in
00148 );
00149 end component;
00150
00151 signal dq_in : ;
00152 signal dq_out : ;
00153 signal dq_delayed : ;
00154 signal write_en_L : ;
00155 signal write_en_L_r1 : ;
00156 signal vcc : ;
00157 signal gnd : ;
00158
00159 begin
00160
00161 vcc <= '1';
00162 gnd <= '0';
00163 write_en_L <= not CTRL_WREN;
00164
00165
00166 oddr_dq : ODDR
00167 generic map (
00168 DDR_CLK_EDGE => "SAME_EDGE",
00169 SRTYPE => "SYNC"
00170 )
00171 port map (
00172 Q => dq_out ,
00173 C => CLK90 ,
00174 CE => vcc ,
00175 D1 => WRITE_DATA_RISE,
00176 D2 => WRITE_DATA_Fall,
00177 R => RESET ,
00178 S => gnd
00179 );
00180
00181
00182 tri_state_dq : FDCE
00183 port map (
00184 D => write_en_L,
00185 CLR => RESET,
00186 C => CLK90 ,
00187 Q => write_en_L_r1,
00188 CE => vcc
00189 );
00190
00191
00192 iobuf_dq : IOBUF
00193 port map (
00194 I => dq_out ,
00195 T => write_en_L_r1,
00196 IO => DDR_DQ ,
00197 O => dq_in
00198 );
00199
00200
00201 idelay_dq : IDELAY
00202 generic map (
00203 IOBDELAY_TYPE => "VARIABLE",
00204 IOBDELAY_VALUE => 0
00205 )
00206 port map (
00207 O => dq_delayed,
00208 I => dq_in ,
00209 C => CAL_CLK ,
00210 CE => DATA_DLYCE,
00211 INC => DATA_DLYINC,
00212 RST => DATA_DLYRST
00213 );
00214
00215
00216 iddr_dq : IDDR
00217 generic map(
00218 DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
00219 SRTYPE => "SYNC"
00220 )
00221 port map (
00222 Q1 => READ_DATA_RISE,
00223 Q2 => READ_DATA_Fall,
00224 C => CLK ,
00225 CE => vcc ,
00226 D => dq_delayed,
00227 R => RESET ,
00228 S => gnd
00229 );
00230
00231 end arc_v4_dq_iob;
00232
00233
00234