BCM-AAA: ddr2_mem_top_0.vhd Source File

00001 --**************************************************************
00002 --*                                                            *
00003 --*     The source code for the ATLAS BCM "AAA" FPGA is made   *
00004 --*     available via the GNU General Public License (GPL)     *
00005 --*     unless otherwise stated below.                         *
00006 --*                                                            *
00007 --*     In case of problems/questions/bug reports etc. please  *
00008 --*     contact michael.niegl@cern.ch                          *
00009 --*                                                            *
00010 --**************************************************************
00011 
00012 --**************************************************************
00013 --*                                                            *
00014 --*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr2/ddr2_mem_top_0.vhd,v $
00015 --*  $Revision: 1.4.2.4 $                                      *
00016 --*  $Name: dev $                                                 *
00017 --*  $Author: mniegl $                                         *
00018 --*  $Date: 2008/11/03 18:48:14 $                              *
00019 
00020 
00021 --*                                                            *
00022 --**************************************************************
00023 -------------------------------------------------------------------------------
00024 -- Copyright (c) 2005 Xilinx, Inc.
00025 -- This design is confidential and proprietary of Xilinx, All Rights Reserved.
00026 -------------------------------------------------------------------------------
00027 --   ____  ____
00028 --  /   /\/   /
00029 -- /___/  \  / Vendor: Xilinx
00030 -- \   \   \/ Version: 1.6
00031 --  \   \ Application : MIG
00032 --  /   / Filename: ddr2_mem_top_0.vhd
00033 -- /___/   /\ Date Last Modified:  Wed Jun 1 2005
00034 -- \   \  /  \Date Created: Mon May 2 2005
00035 --  \___\/\___\
00036 -- 
00037 -- Device: Virtex-4
00038 -- Design Name: DDR2_V4
00039 -------------------------------------------------------------------------------
00040 
00041 
00042 library ieee;
00043 
00044 use ieee.std_logic_1164.all;
00045 
00046 use ieee.std_logic_unsigned.all;
00047 
00048 use ieee.numeric_std.all;
00049 library work;
00050 use work.ddr2_mem_parameters_0.all;
00051 
00052 library unisim;
00053 
00054 use unisim.vcomponents.all;
00055 
00056 
00057 
00058 
00059 entity ddr2_mem_top_0 is
00060   port (
00061     clk_0              : in    std_logic;
00062     clk_90             : in    std_logic;
00063     clk_50             : in    std_logic;
00064     ref_clk            : in    std_logic;
00065     sys_rst            : in    std_logic;
00066     sys_rst90          : in    std_logic;
00067     sys_rst_ref_clk_1  : in    std_logic;
00068     DDR2_RESET_N       : out   std_logic;
00069     idelay_ctrl_rdy    : in    std_logic;
00070     DDR2_RAS_N         : out   std_logic;
00071     DDR2_CAS_N         : out   std_logic;
00072     DDR2_WE_N          : out   std_logic;
00073     DDR2_ODT           : out   std_logic;
00074     DDR2_CKE           : out   std_logic;
00075     DDR2_CS_N          : out   std_logic;
00076     DDR2_DQ            : inout std_logic_vector(data_width-1 downto 0);
00077     DDR2_DQS           : inout std_logic_vector(data_strobe_width-1 downto 0);
00078     DDR2_DQS_N         : inout std_logic_vector(data_strobe_width-1 downto 0);
00079     DDR2_DM            : out   std_logic_vector(data_mask_width-1 downto 0);
00080     DDR2_CK            : out   std_logic;
00081     DDR2_CK_N          : out   std_logic;
00082     DDR2_BA            : out   std_logic_vector(bank_address-1 downto 0);
00083     DDR2_A             : out   std_logic_vector(row_address-1 downto 0);
00084     WDF_ALMOST_FULL    : out   std_logic;
00085     AF_ALMOST_FULL     : out   std_logic;
00086     BURST_LENGTH       : out   std_logic_vector(2 downto 0);
00087     READ_DATA_VALID    : out   std_logic;
00088     READ_DATA_FIFO_OUT : out   std_logic_vector(dq_width*2-1 downto 0);
00089     APP_AF_ADDR        : in    std_logic_vector(35 downto 0);
00090     APP_AF_WREN        : in    std_logic;
00091     APP_WDF_DATA       : in    std_logic_vector(dq_width*2-1 downto 0);
00092     APP_MASK_DATA      : in    std_logic_vector(dm_width*2-1 downto 0);
00093     APP_WDF_WREN       : in    std_logic;
00094     CLK_TB             : out   std_logic;
00095     RESET_TB           : out   std_logic
00096     );
00097 end entity;
00098 
00099 
00100 
00101 
00102 architecture arc_top of ddr2_mem_top_0 is
00103 
00104 
00105   component ddr2_mem_data_path_0
00106     port (
00107       CLK                  : in  std_logic;
00108       CLK90                : in  std_logic;
00109       CAL_CLK              : in  std_logic;
00110       RESET0               : in  std_logic;
00111       RESET90              : in  std_logic;
00112       RESET_CAL_CLK        : in  std_logic;
00113       CTRL_DUMMYREAD_START : in  std_logic;
00114       idelay_ctrl_rdy      : in  std_logic;
00115       WDF_DATA             : in  std_logic_vector(dq_width*2-1 downto 0);
00116       MASK_DATA            : in  std_logic_vector(dm_width*2-1 downto 0);
00117       CTRL_WREN            : in  std_logic;
00118       CTRL_DQS_RST         : in  std_logic;
00119       CTRL_DQS_EN          : in  std_logic;
00120       CTRL_DUMMY_WR_SEL    : in  std_logic;
00121       dummy_write_flag     : in  std_logic;
00122       dqs_delayed          : in  std_logic_vector(data_strobe_width-1 downto 0);
00123       wr_data_rise         : out std_logic_vector(data_width-1 downto 0);
00124       wr_data_fall         : out std_logic_vector(data_width-1 downto 0);
00125       mask_data_rise       : out std_logic_vector(data_mask_width-1 downto 0);
00126       mask_data_fall       : out std_logic_vector(data_mask_width-1 downto 0);
00127       wr_en                : out std_logic;
00128       dqs_rst              : out std_logic;
00129       dqs_en               : out std_logic;
00130       dqs_idelay_inc       : out std_logic_vector(ReadEnable-1 downto 0);
00131       dqs_idelay_ce        : out std_logic_vector(ReadEnable-1 downto 0);
00132       dqs_idelay_rst       : out std_logic_vector(ReadEnable-1 downto 0);
00133 
00134       data_idelay_inc : out std_logic_vector(ReadEnable-1 downto 0);
00135       data_idelay_ce  : out std_logic_vector(ReadEnable-1 downto 0);
00136       data_idelay_rst : out std_logic_vector(ReadEnable-1 downto 0);
00137 
00138       SEL_DONE : out std_logic
00139       );
00140 
00141   end component;
00142 
00143 
00144   component ddr2_mem_iobs_0
00145     port (
00146       CLK               : in    std_logic;
00147       CLK90             : in    std_logic;
00148       DDR_CK            : out   std_logic;
00149       DDR_CK_N          : out   std_logic;
00150       CAL_CLK           : in    std_logic;
00151       RESET0            : in    std_logic;
00152       RESET90           : in    std_logic;
00153       dqs_idelay_inc    : in    std_logic_vector(ReadEnable-1 downto 0);
00154       dqs_idelay_ce     : in    std_logic_vector(ReadEnable-1 downto 0);
00155       dqs_idelay_rst    : in    std_logic_vector(ReadEnable-1 downto 0);
00156       dqs_rst           : in    std_logic;
00157       dqs_en            : in    std_logic;
00158       wr_en             : in    std_logic;
00159       dqs_delayed       : out   std_logic_vector(data_strobe_width-1 downto 0);
00160       data_idelay_inc   : in    std_logic_vector(ReadEnable-1 downto 0);
00161       data_idelay_ce    : in    std_logic_vector(ReadEnable-1 downto 0);
00162       data_idelay_rst   : in    std_logic_vector(ReadEnable-1 downto 0);
00163       wr_data_rise      : in    std_logic_vector(data_width-1 downto 0);
00164       wr_data_fall      : in    std_logic_vector(data_width-1 downto 0);
00165       mask_data_rise    : in    std_logic_vector(data_mask_width-1 downto 0);
00166       mask_data_fall    : in    std_logic_vector(data_mask_width-1 downto 0);
00167       rd_data_rise      : out   std_logic_vector(data_width-1 downto 0);
00168       rd_data_fall      : out   std_logic_vector(data_width-1 downto 0);
00169       DDR_DQ            : inout std_logic_vector(data_width-1 downto 0);
00170       DDR_DQS           : inout std_logic_vector(data_strobe_width-1 downto 0);
00171       DDR_DQS_L         : inout std_logic_vector(data_strobe_width-1 downto 0);
00172       DDR_DM            : out   std_logic_vector(data_mask_width-1 downto 0);
00173       DDR_ADDRESS       : out   std_logic_vector(row_address-1 downto 0);
00174       DDR_BA            : out   std_logic_vector(bank_address-1 downto 0);
00175       DDR_RAS_L         : out   std_logic;
00176       DDR_CAS_L         : out   std_logic;
00177       DDR_WE_L          : out   std_logic;
00178       DDR_cs_L          : out   std_logic;
00179       DDR_CKE           : out   std_logic;
00180       DDR_ODT           : out   std_logic;
00181       ctrl_ddr2_ras_L   : in    std_logic;
00182       ctrl_ddr2_cas_L   : in    std_logic;
00183       ctrl_ddr2_we_L    : in    std_logic;
00184       ctrl_ddr2_odt     : in    std_logic;
00185       ctrl_ddr2_cke     : in    std_logic;
00186       ctrl_ddr2_cs_L    : in    std_logic;
00187       ctrl_ddr2_ba      : in    std_logic_vector(bank_address-1 downto 0);
00188       ctrl_ddr2_address : in    std_logic_vector(row_address-1 downto 0)
00189       );
00190   end component;
00191 
00192 
00193   component ddr2_mem_user_interface_0
00194     port (
00195       CLK                : in  std_logic;
00196       clk90              : in  std_logic;
00197       RESET              : in  std_logic;
00198       READ_DATA_RISE     : in  std_logic_vector(data_width-1 downto 0);
00199       READ_DATA_Fall     : in  std_logic_vector(data_width-1 downto 0);
00200       APP_AF_ADDR        : in  std_logic_vector(35 downto 0);
00201       APP_AF_WREN        : in  std_logic;
00202       CTRL_AF_RDEN       : in  std_logic;
00203       APP_WDF_DATA       : in  std_logic_vector(dq_width*2-1 downto 0);
00204       APP_MASK_DATA      : in  std_logic_vector(dm_width*2-1 downto 0);
00205       APP_WDF_WREN       : in  std_logic;
00206       CTRL_WDF_RDEN      : in  std_logic;
00207       CTRL_RDEN          : in  std_logic;
00208       COMP_DONE          : out std_logic;
00209       READ_DATA_FIFO_OUT : out std_logic_vector(dq_width*2-1 downto 0);
00210       READ_DATA_VALID    : out std_logic;
00211       AF_ADDR            : out std_logic_vector(35 downto 0);
00212       WDF_DATA           : out std_logic_vector(dq_width*2-1 downto 0);
00213       MASK_DATA          : out std_logic_vector(dm_width*2-1 downto 0);
00214       WDF_ALMOST_FULL    : out std_logic;
00215       AF_ALMOST_FULL     : out std_logic;
00216       AF_EMPTY           : out std_logic
00217       );
00218   end component;
00219 
00220 
00221   component ddr2_mem_ddr2_controller_0
00222     port (
00223       clk0                 : in  std_logic;
00224       refresh_clk          : in  std_logic;
00225       rst                  : in  std_logic;
00226       af_addr              : in  std_logic_vector(35 downto 0);
00227       af_empty             : in  std_logic;
00228       phy_Dly_Slct_Done    : in  std_logic;
00229       COMP_DONE            : in  std_logic;
00230       ctrl_dummy_wr_sel    : out std_logic;
00231       burst_length         : out std_logic_vector(2 downto 0);
00232       ctrl_Dummyread_Start : out std_logic;
00233       ctrl_af_RdEn         : out std_logic;
00234       ctrl_Wdf_RdEn        : out std_logic;
00235       ctrl_Dqs_Rst         : out std_logic;
00236       ctrl_Dqs_En          : out std_logic;
00237       ctrl_WrEn            : out std_logic;
00238       ctrl_RdEn            : out std_logic;
00239       ctrl_ddr2_address    : out std_logic_vector((row_address-1) downto 0);
00240       ctrl_ddr2_ba         : out std_logic_vector((bank_address-1) downto 0);
00241       ctrl_ddr2_ras_L      : out std_logic;
00242       ctrl_ddr2_cas_L      : out std_logic;
00243       ctrl_ddr2_we_L       : out std_logic;
00244       ctrl_ddr2_cs_L       : out std_logic;
00245       ctrl_ddr2_cke        : out std_logic;
00246       ctrl_ddr2_odt        : out std_logic;
00247       dummy_write_flag     : out std_logic
00248       );
00249   end component;
00250 
00251   signal wr_df_data        : std_logic_vector(dq_width*2-1 downto 0);
00252   signal mask_df_data      : std_logic_vector(dm_width*2-1 downto 0);
00253   signal rd_data_rise      : std_logic_vector(data_width-1 downto 0);
00254   signal rd_data_fall      : std_logic_vector(data_width-1 downto 0);
00255   signal af_empty_w        : std_logic;
00256   signal dq_tap_sel_done   : std_logic;
00257   signal af_addr           : std_logic_vector(35 downto 0);
00258   signal ctrl_af_rden      : std_logic;
00259   signal ctrl_wr_df_rden   : std_logic;
00260   signal ctrl_dummy_rden   : std_logic;
00261   signal ctrl_dqs_enable   : std_logic;
00262   signal ctrl_dqs_reset    : std_logic;
00263   signal ctrl_wr_en        : std_logic;
00264   signal ctrl_rden         : std_logic;
00265   signal dqs_idelay_inc    : std_logic_vector(ReadEnable-1 downto 0);
00266   signal dqs_idelay_ce     : std_logic_vector(ReadEnable-1 downto 0);
00267   signal dqs_idelay_rst    : std_logic_vector(ReadEnable-1 downto 0);
00268   signal data_idelay_inc   : std_logic_vector(ReadEnable-1 downto 0);
00269   signal data_idelay_ce    : std_logic_vector(ReadEnable-1 downto 0);
00270   signal data_idelay_rst   : std_logic_vector(ReadEnable-1 downto 0);
00271   signal dqs_rst           : std_logic;
00272   signal dqs_en            : std_logic;
00273   signal wr_en             : std_logic;
00274   signal wr_data_rise      : std_logic_vector((data_width-1) downto 0);
00275   signal wr_data_fall      : std_logic_vector((data_width-1) downto 0);
00276   signal dqs_delayed       : std_logic_vector((data_strobe_width-1) downto 0);
00277   signal mask_data_rise    : std_logic_vector(data_mask_width-1 downto 0);
00278   signal mask_data_fall    : std_logic_vector(data_mask_width-1 downto 0);
00279   signal ctrl_ddr2_address : std_logic_vector(row_address-1 downto 0);
00280   signal ctrl_ddr2_ba      : std_logic_vector(bank_address-1 downto 0);
00281   signal ctrl_ddr2_ras_L   : std_logic;
00282   signal ctrl_ddr2_cas_L   : std_logic;
00283   signal ctrl_ddr2_we_L    : std_logic;
00284   signal ctrl_ddr2_cs_L    : std_logic;
00285   signal ctrl_ddr2_cke     : std_logic;
00286   signal ctrl_ddr2_odt     : std_logic;
00287   signal DDR2_DM_r         : std_logic_vector(data_mask_width-1 downto 0);
00288   signal ctrl_dummy_wr_sel : std_logic;
00289   signal COMP_DONE         : std_logic;
00290   signal dummy_write_flag  : std_logic;
00291 
00292 begin
00293 
00294   CLK_TB       <= clk_0;
00295   RESET_TB     <= sys_rst;
00296   DDR2_DM      <= DDR2_DM_r;
00297   DDR2_RESET_N <= not sys_rst;
00298 
00299 
00300   data_path_00 : ddr2_mem_data_path_0
00301     port map (
00302       CLK                   => clk_0,
00303       CLK90                 => clk_90,
00304       CAL_CLK               => clk_50,
00305       RESET0                => sys_rst,
00306       RESET90              => sys_rst90,
00307       RESET_CAL_CLK        => sys_rst_ref_clk_1 ,
00308       CTRL_DUMMYREAD_START => ctrl_dummy_rden,
00309       idelay_ctrl_rdy      => idelay_ctrl_rdy,
00310       WDF_DATA             => wr_df_data,
00311       MASK_DATA            => mask_df_data,
00312       CTRL_WREN            => ctrl_wr_en,
00313       CTRL_DQS_RST         => ctrl_dqs_reset,
00314       CTRL_DQS_EN          => ctrl_dqs_enable ,
00315       DQS_DELAYED          => dqs_delayed,
00316       CTRL_DUMMY_WR_SEL    => ctrl_dummy_wr_sel,
00317       data_idelay_inc      => data_idelay_inc,
00318       data_idelay_ce       => data_idelay_ce,
00319       data_idelay_rst      => data_idelay_rst,
00320       dqs_idelay_inc       => dqs_idelay_inc,
00321       dqs_idelay_ce        => dqs_idelay_ce,
00322       dqs_idelay_rst       => dqs_idelay_rst,
00323       SEL_DONE             => dq_tap_sel_done ,
00324       dqs_rst              => dqs_rst,
00325       dqs_en               => dqs_en,
00326       wr_en                => wr_en,
00327       wr_data_rise         => wr_data_rise,
00328       wr_data_fall         => wr_data_fall,
00329       mask_data_rise       => mask_data_rise,
00330       mask_data_fall       => mask_data_fall,
00331       dummy_write_flag     => dummy_write_flag
00332       );
00333 
00334 
00335   iobs_00 : ddr2_mem_iobs_0
00336     port map (
00337       CLK               => clk_0,
00338       CLK90             => clk_90,
00339       CAL_CLK           => clk_50,
00340       RESET0            => sys_rst,
00341       RESET90           => sys_rst90,
00342       DDR_CK            => DDR2_CK,
00343       DDR_CK_N          => DDR2_CK_N,
00344       data_idelay_inc   => data_idelay_inc,
00345       data_idelay_ce    => data_idelay_ce,
00346       data_idelay_rst   => data_idelay_rst,
00347       dqs_idelay_inc    => dqs_idelay_inc,
00348       dqs_idelay_ce     => dqs_idelay_ce,
00349       dqs_idelay_rst    => dqs_idelay_rst,
00350       dqs_rst           => dqs_rst,
00351       dqs_en            => dqs_en,
00352       wr_en             => wr_en,
00353       wr_data_rise      => wr_data_rise,
00354       wr_data_fall      => wr_data_fall,
00355       mask_data_rise    => mask_data_rise,
00356       mask_data_fall    => mask_data_fall,
00357       rd_data_rise      => rd_data_rise,
00358       rd_data_fall      => rd_data_fall,
00359       dqs_delayed       => dqs_delayed,
00360       DDR_DQ            => DDR2_DQ,
00361       DDR_DQS           => DDR2_DQS,
00362       DDR_DQS_L         => DDR2_DQS_N,
00363       DDR_DM            => DDR2_DM_r,
00364       ctrl_ddr2_address => ctrl_ddr2_address,
00365       ctrl_ddr2_ba      => ctrl_ddr2_ba,
00366       ctrl_ddr2_ras_L   => ctrl_ddr2_ras_L,
00367       ctrl_ddr2_cas_L   => ctrl_ddr2_cas_L,
00368       ctrl_ddr2_we_L    => ctrl_ddr2_we_L,
00369       ctrl_ddr2_cs_L    => ctrl_ddr2_cs_L,
00370       ctrl_ddr2_cke     => ctrl_ddr2_cke,
00371       ctrl_ddr2_odt     => ctrl_ddr2_odt,
00372       DDR_ADDRESS       => DDR2_A,
00373       DDR_BA            => DDR2_BA,
00374       DDR_RAS_L         => DDR2_RAS_N,
00375       DDR_CAS_L         => DDR2_CAS_N,
00376       DDR_WE_L          => DDR2_WE_N,
00377       DDR_CKE           => DDR2_CKE,
00378       DDR_ODT           => DDR2_ODT,
00379       DDR_cs_L          => DDR2_CS_N
00380       );
00381 
00382 
00383   user_interface_00 : ddr2_mem_user_interface_0
00384     port map (
00385       CLK                 => clk_0,
00386       clk90               => clk_90,
00387       RESET              => sys_rst,
00388       CTRL_RDEN          => ctrl_rden,
00389       COMP_DONE          => COMP_DONE,
00390       READ_DATA_RISE     => rd_data_rise,
00391       READ_DATA_Fall     => rd_data_fall,
00392       READ_DATA_FIFO_OUT => READ_DATA_FIFO_OUT,
00393       READ_DATA_VALID    => READ_DATA_VALID,
00394       AF_EMPTY           => af_empty_w,
00395       AF_ALMOST_FULL     => AF_ALMOST_FULL,
00396       APP_AF_ADDR        => APP_AF_ADDR,
00397       APP_AF_WREN        => APP_AF_WREN,
00398       CTRL_AF_RDEN       => ctrl_af_rden,
00399       AF_ADDR            => af_addr,
00400       APP_WDF_DATA       => APP_WDF_DATA,
00401       APP_MASK_DATA      => APP_MASK_DATA,
00402       APP_WDF_WREN       => APP_WDF_WREN,
00403       CTRL_WDF_RDEN      => ctrl_wr_df_rden,
00404       WDF_DATA           => wr_df_data,
00405       MASK_DATA          => mask_df_data,
00406       WDF_ALMOST_FULL    => WDF_ALMOST_FULL
00407       );
00408 
00409 
00410   ddr2_controller_00 : ddr2_mem_ddr2_controller_0
00411     port map (
00412       clk0                  => clk_0,
00413       refresh_clk          => ref_clk,
00414       rst                   => sys_rst,
00415       burst_length          => BURST_LENGTH,
00416       af_addr               => af_addr,
00417       af_empty             => af_empty_w,
00418       phy_Dly_Slct_Done    => dq_tap_sel_done,
00419       ctrl_Dummyread_Start => ctrl_dummy_rden,
00420       ctrl_af_RdEn         => ctrl_af_rden,
00421       ctrl_Wdf_RdEn        => ctrl_wr_df_rden,
00422       ctrl_Dqs_Rst         => ctrl_dqs_reset,
00423       ctrl_Dqs_En          => ctrl_dqs_enable ,
00424       ctrl_WrEn            => ctrl_wr_en,
00425       ctrl_RdEn            => ctrl_rden,
00426       ctrl_ddr2_address    => ctrl_ddr2_address,
00427       ctrl_ddr2_ba         => ctrl_ddr2_ba,
00428       ctrl_ddr2_ras_L      => ctrl_ddr2_ras_L,
00429       ctrl_ddr2_cas_L      => ctrl_ddr2_cas_L,
00430       ctrl_ddr2_we_L       => ctrl_ddr2_we_L,
00431       ctrl_ddr2_cs_L       => ctrl_ddr2_cs_L,
00432       ctrl_ddr2_cke        => ctrl_ddr2_cke,
00433       ctrl_ddr2_odt        => ctrl_ddr2_odt,
00434       ctrl_dummy_wr_sel    => ctrl_dummy_wr_sel,
00435       COMP_DONE            => COMP_DONE,
00436       dummy_write_flag     => dummy_write_flag
00437       ); 
00438 
00439 end arc_top;