ram_user_backend.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr/ram_user_backend.vhd,v $
--*  $Revision: 1.15.2.3 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:44 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

library unisim;

use unisim.vcomponents.all;
library work;

use work.mem_interface_top_parameters_0.all;




entity ram_user_backend is
  port
    (
      cntrl0_DDR_DQ    : inout std_logic_vector(31 downto 0);
      cntrl0_DDR_A     : out   std_logic_vector(12 downto 0);
      cntrl0_DDR_BA    : out   std_logic_vector(1 downto 0);
      cntrl0_DDR_CKE   : out   std_logic;
      cntrl0_DDR_CS_N  : out   std_logic;
      cntrl0_DDR_RAS_N : out   std_logic;
      cntrl0_DDR_CAS_N : out   std_logic;
      cntrl0_DDR_WE_N  : out   std_logic;
      cntrl0_DDR_DM    : out   std_logic_vector(3 downto 0);
      cntrl0_DDR_DQS   : inout std_logic_vector(3 downto 0);
      cntrl0_DDR_CK    : out   std_logic;
      cntrl0_DDR_CK_N  : out   std_logic;
      SYSCLK_P         : in    std_logic;
      SYSCLK_N         : in    std_logic;
      CLK200_P         : in    std_logic;
      CLK200_N         : in    std_logic;
      SYS_RESET_IN     : in    std_logic;
      ADDR_RES         : in    std_logic;
      ADDR_OVR         : out   std_logic;
      R_W              : in    std_logic;
      LED_CONTR        : out   std_logic;
      LED_R            : out   std_logic;
      EN               : in    std_logic;
      HALT             : out   std_logic;
      VALID_OUT        : out   std_logic;
      RDBURST_END      : out   std_logic;
      DATA_IN          : in    std_logic_vector(63 downto 0);
      READ_DATA_OUT    : out   std_logic_vector(63 downto 0)
      );                        

end ram_user_backend;






architecture ram_user_backend_arc of ram_user_backend is

--*************************** Signal Declarations *****************************
  signal sysclk_p_i        : std_logic                     := '0';
  signal sysclk_n_i        : std_logic                     := '0';
  signal clk200_p_i        : std_logic                     := '0';
  signal clk200_n_i        : std_logic                     := '0';
  signal clk_tb            : std_logic                     := '0';
  signal clk_buf           : std_logic                     := '0';
  signal CS                : std_logic                     := '0';
  signal addr_en           : std_logic                     := '0';
  signal data_en           : std_logic                     := '0';
  signal nop_en            : std_logic                     := '0';
  signal addr_full         : std_logic                     := '0';
  signal data_full         : std_logic                     := '0';
  signal read_valid        : std_logic                     := '0';
  signal sys_res           : std_logic                     := '0';
  signal halt_i            : std_logic                     := '0';
  signal lock_i            : std_logic                     := '0';
  signal data_out          : std_logic_vector(63 downto 0) := (others => '0');
  signal block_start       : std_logic_vector(2 downto 0)  := (others => '0');
  signal command           : std_logic_vector(2 downto 0)  := (others => '0');
  signal cmd               : std_logic_vector(2 downto 0)  := (others => '0');
  signal nop               : std_logic_vector(2 downto 0)  := (others => '0');
  signal address_vec       : std_logic_vector(35 downto 0) := (others => '0');
  signal bank_sel          : std_logic_vector(1 downto 0)  := (others => '0');
  signal row_sel           : std_logic_vector(12 downto 0) := (others => '0');
  signal column_sel        : std_logic_vector(5 downto 0)  := (others => '0');
  signal burst_cnt         : std_logic_vector(1 downto 0)  := (others => '0');
  signal nop_cnt           : std_logic_vector(1 downto 0)  := (others => '0');
  signal mask              : std_logic_vector(7 downto 0)  := (others => '0');
  signal cntrl0_DDR_CK_i   : std_logic_vector(1 downto 0)  := (others => '0');
  signal cntrl0_DDR_CK_N_i : std_logic_vector(1 downto 0)  := (others => '0');

--************************** Component Declarations ***************************

  component mem_interface_top
    port(
      SYS_CLK_P                 : in    std_logic;
      SYS_CLK_N                 : in    std_logic;
      CLK200_P                  : in    std_logic;
      CLK200_N                  : in    std_logic;
      CLK200                    : out   std_logic;
      SYS_RESET_IN              : in    std_logic;
      LOCK                      : in    std_logic;
      cntrl0_APP_WDF_WREN       : in    std_logic;
      cntrl0_APP_AF_WREN        : in    std_logic;
      cntrl0_APP_AF_ADDR        : in    std_logic_vector(35 downto 0);
      cntrl0_APP_WDF_DATA       : in    std_logic_vector(63 downto 0);
      cntrl0_APP_MASK_DATA      : in    std_logic_vector(7 downto 0);
      cntrl0_DDR_DQ             : inout std_logic_vector(31 downto 0);
      cntrl0_DDR_DQS            : inout std_logic_vector(3 downto 0);
      cntrl0_DDR_A              : out   std_logic_vector(12 downto 0);
      cntrl0_DDR_BA             : out   std_logic_vector(1 downto 0);
      cntrl0_DDR_CKE            : out   std_logic;
      cntrl0_DDR_CS_N           : out   std_logic;
      cntrl0_DDR_RAS_N          : out   std_logic;
      cntrl0_DDR_CAS_N          : out   std_logic;
      cntrl0_DDR_WE_N           : out   std_logic;
      cntrl0_DDR_DM             : out   std_logic_vector(3 downto 0);
      cntrl0_CLK_TB             : out   std_logic;
      cntrl0_RESET_TB           : out   std_logic;
      cntrl0_WDF_ALMOST_FULL    : out   std_logic;
      cntrl0_AF_ALMOST_FULL     : out   std_logic;
      cntrl0_READ_DATA_VALID    : out   std_logic;
      cntrl0_BURST_LENGTH       : out   std_logic_vector(2 downto 0);
      cntrl0_READ_DATA_FIFO_OUT : out   std_logic_vector(63 downto 0);
      cntrl0_DDR_CK             : out   std_logic_vector(1 downto 0);
      cntrl0_DDR_CK_N           : out   std_logic_vector(1 downto 0)
      );
  end component;


  component BUFG
    port(
      O : out std_logic;
      I : in  std_logic
      );
  end component;

--*************************************************************************
--*                               main code
--*************************************************************************

begin
  
  LED_CONTR <= '1' when sys_res = '1' else '0';

  sys_res <= SYS_RESET_IN when rising_edge(sysclk_p_i);
  lock_i  <= not SYS_RESET_IN;

  LED_R      <= '1' when R_W = '1' else '0';
  sysclk_p_i <= SYSCLK_P;
  sysclk_n_i <= SYSCLK_N;
  clk200_p_i <= CLK200_P;
  clk200_n_i <= CLK200_N;

  VALID_OUT     <= read_valid            when rising_edge(clk_buf);
  READ_DATA_OUT <= data_out              when rising_edge(clk_buf);
  halt_i        <= (data_full or nop_en) when R_W = '0' else '1';
  HALT          <= not halt_i            when rising_edge(clk_buf);
  address_vec   <= '0' & command & "00000" & CS & bank_sel & row_sel & "00" & column_sel & block_start;
  ADDR_OVR      <= '0' when SYS_RESET_IN = '1' else
                   '1' when bank_sel = "11" and row_sel = "1111111111111" and column_sel = "111111" else
                   '0';
  CS          <= '0';
  mask        <= (others => '0');
  block_start <= "000";  -- always start burst writes at position zero of block
  nop         <= "111";
  command     <= nop when nop_en = '1' else
                 cmd;
  cmd <= "101" when R_W = '1' else      -- read command
         "100";                         -- write command
  RDBURST_END <= nop_en when R_W = '1' else '0';


  control_data_enable : process(clk_buf)
  begin
    if clk_buf'event and clk_buf = '1' then
      if R_W = '0' and data_full = '0' and nop_en = '0' then
        data_en <= '1';
      else
        data_en <= '0';
      end if;
    end if;
  end process control_data_enable;





  addr_gen : process(clk_buf)
  begin
    if clk_buf'event and clk_buf = '1' then
      
      if (sys_res or ADDR_RES) = '1' then
        column_sel <= (others => '0');
        bank_sel   <= (others => '0');
        row_sel    <= (others => '0');
        burst_cnt  <= "00";
        nop_cnt    <= "00";
        addr_en    <= '0';
        nop_en     <= '0';
        
      elsif addr_full = '0' and EN = '1' then  --stop_write = '0' then

        burst_cnt <= burst_cnt + 1;

        if R_W = '0' and data_full = '0' then
          
          if burst_cnt = "11" then
            if nop_en = '1' then
              addr_en <= '0';
            else
              addr_en <= '1';
            end if;
            nop_cnt <= nop_cnt + 1;
          else
            addr_en <= '0';
            nop_cnt <= nop_cnt;
          end if;

          if burst_cnt = "10" then
            if nop_cnt = "11" then
              nop_en     <= '1';
              bank_sel   <= bank_sel;
              column_sel <= column_sel;
              row_sel    <= row_sel;
            else
              nop_en <= '0';
            end if;
          end if;

          if nop_en = '0' then
            if burst_cnt = "11" then
              column_sel <= column_sel + 1;
              if column_sel = "111111" then
                bank_sel   <= bank_sel + 1;
                column_sel <= (others => '0');
                if bank_sel = "11" then
                  row_sel  <= row_sel + 1;
                  bank_sel <= "00";
                  
                else
                  row_sel <= row_sel;
                end if;
              else
                bank_sel <= bank_sel;
              end if;
            else
              column_sel <= column_sel;
            end if;
          end if;
          
        else
          
          if burst_cnt = "11" then
            if nop_en = '1' then
              addr_en <= '0';
            else
              addr_en <= '1';
            end if;
            nop_en <= not nop_en;
          else
            addr_en <= '0';
            nop_cnt <= nop_cnt;
          end if;

          if nop_en = '0' then
            if burst_cnt = "11" then
              column_sel <= column_sel + 1;
              if column_sel = "111111" then
                bank_sel   <= bank_sel + 1;
                column_sel <= (others => '0');
                if bank_sel = "11" then
                  row_sel  <= row_sel + 1;
                  bank_sel <= "00";
                else
                  row_sel <= row_sel;
                end if;
              else
                bank_sel <= bank_sel;
              end if;
            else
              column_sel <= column_sel;
            end if;
          end if;
          
        end if;

      elsif R_W = '0' and EN = '0' then
        addr_en <= '0';
        nop_en  <= '0';
        nop_cnt <= (others => '0');
        
      else
        
        addr_en <= '0';
        
      end if;
    end if;
  end process addr_gen;


  RAM_controller : mem_interface_top
    port map
    (
      cntrl0_DDR_DQ             => cntrl0_DDR_DQ,
      cntrl0_DDR_A              => cntrl0_DDR_A,
      cntrl0_DDR_BA             => cntrl0_DDR_BA,
      cntrl0_DDR_CKE            => cntrl0_DDR_CKE,
      cntrl0_DDR_CS_N           => cntrl0_DDR_CS_N,
      cntrl0_DDR_RAS_N          => cntrl0_DDR_RAS_N,
      cntrl0_DDR_CAS_N          => cntrl0_DDR_CAS_N,
      cntrl0_DDR_WE_N           => cntrl0_DDR_WE_N,
      cntrl0_DDR_DM             => cntrl0_DDR_DM,
      SYS_CLK_P                 => SYSCLK_P_i,
      SYS_CLK_N                 => SYSCLK_N_i,
      CLK200_P                  => CLK200_P_i,
      CLK200_N                  => CLK200_N_i,
      CLK200                    => open,
      SYS_RESET_IN              => sys_res,
      LOCK                      => lock_i,
      cntrl0_CLK_TB             => clk_tb,
      cntrl0_RESET_TB           => open,
      cntrl0_WDF_ALMOST_FULL    => data_full,
      cntrl0_AF_ALMOST_FULL     => addr_full,
      cntrl0_READ_DATA_VALID    => read_valid,
      cntrl0_APP_WDF_WREN       => data_en,
      cntrl0_APP_AF_WREN        => addr_en,
      cntrl0_BURST_LENGTH       => open,
      cntrl0_APP_AF_ADDR        => address_vec,
      cntrl0_APP_WDF_DATA       => DATA_IN,
      cntrl0_READ_DATA_FIFO_OUT => data_out,
      cntrl0_APP_MASK_DATA      => mask,
      cntrl0_DDR_DQS            => cntrl0_DDR_DQS,
      cntrl0_DDR_CK             => cntrl0_DDR_CK_i,
      cntrl0_DDR_CK_N           => cntrl0_DDR_CK_N_i
      );

  cntrl0_DDR_CK   <= cntrl0_DDR_CK_i(1);
  cntrl0_DDR_CK_N <= cntrl0_DDR_CK_N_i(1);
  clk_buf         <= clk_tb;


--  BUFG_clk_tb : BUFG
--    port map (
--      O => clk_buf,                     -- Clock buffer output
--      I => clk_tb                       -- Clock buffer input
--      );

end ram_user_backend_arc;

---

Author: M.Niegl

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