BCM-AAA: bcm_aaa.vhd Source File

00001 --**************************************************************
00002 --*                                                            *
00003 --*     The source code for the ATLAS BCM "AAA" FPGA is made   *
00004 --*     available via the GNU General Public License (GPL)     *
00005 --*     unless otherwise stated below.                         *
00006 --*                                                            *
00007 --*     In case of problems/questions/bug reports etc. please  *
00008 --*     contact michael.niegl@cern.ch                          *
00009 --*                                                            *
00010 --**************************************************************
00011 
00012 --**************************************************************
00013 --*                                                            *
00014 --*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/main/bcm_aaa.vhd,v $
00015 --*  $Revision: 2.35.2.14 $                                         *
00016 --*  $Name: dev $                                                 *
00017 --*  $Author: mniegl $                                         *
00018 --*  $Date: 2008/11/03 19:00:04 $                              *
00019 
00020 
00021 --*                                                            *
00022 --**************************************************************
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00107 library ieee;
00108 
00109 use ieee.std_logic_1164.all;
00110 
00111 use ieee.std_logic_arith.all;
00112 
00113 use ieee.std_logic_unsigned.all;
00114 
00115 use ieee.numeric_std.all;
00116 
00117 library unisim;
00118 
00119 use unisim.vcomponents.all;
00120 
00121 library work;
00122 
00123 use work.main_components.all;
00124 
00125 use work.build_parameters.all;
00126 
00127 
00128 
00129 
00130 
00131 
00132 
00133 
00134 
00135 entity bcm_aaa is
00136   port (
00137 -- Clocks
00138     SYSCLK                   : in    std_logic;
00139     UPPER_MGTCLK_PAD_P_IN_EX : in    std_logic_vector(1 downto 0);
00140     UPPER_MGTCLK_PAD_N_IN_EX : in    std_logic_vector(1 downto 0);
00141     CLK_TOP                  : in    std_logic;
00142     CLK_BOT                  : in    std_logic;
00143     XTAL_SEL                 : out   std_logic;
00144     CLK_DET                  : in    std_logic;
00145 -- Reset
00146     RESET                    : in    std_logic;
00147     SOS_LED                  : out   std_logic;
00148 -- RocketIOs
00149     VALID_all                : out   std_logic;
00150     MASK_IRENA               : out   std_logic;
00151     MASK_EWA                 : out   std_logic;
00152     MASK_ANDREJ              : out   std_logic;
00153     MASK_HEINZ               : out   std_logic;
00154     MASK_MARKO               : out   std_logic;
00155     MASK_WILLIAM             : out   std_logic;
00156     MASK_HARRIS              : out   std_logic;
00157     MASK_HELMUT              : out   std_logic;
00158     RXN_C_IE                 : in    std_logic_vector(1 downto 0);
00159     RXP_C_IE                 : in    std_logic_vector(1 downto 0);
00160     RXN_C_AH                 : in    std_logic_vector(1 downto 0);
00161     RXP_C_AH                 : in    std_logic_vector(1 downto 0);
00162     RXN_A_WM                 : in    std_logic_vector(1 downto 0);
00163     RXP_A_WM                 : in    std_logic_vector(1 downto 0);
00164     RXN_A_HH                 : in    std_logic_vector(1 downto 0);
00165     RXP_A_HH                 : in    std_logic_vector(1 downto 0);
00166     TXN_C_IE                 : out   std_logic_vector(1 downto 0);
00167     TXP_C_IE                 : out   std_logic_vector(1 downto 0);
00168     TXN_C_AH                 : out   std_logic_vector(1 downto 0);
00169     TXP_C_AH                 : out   std_logic_vector(1 downto 0);
00170     TXN_A_WM                 : out   std_logic_vector(1 downto 0);
00171     TXP_A_WM                 : out   std_logic_vector(1 downto 0);
00172     TXN_A_HH                 : out   std_logic_vector(1 downto 0);
00173     TXP_A_HH                 : out   std_logic_vector(1 downto 0);
00174 -- DDR
00175     cntrl0_DDR_A             : out   std_logic_vector(12 downto 0);
00176     cntrl0_DDR_BA            : out   std_logic_vector(1 downto 0);
00177     cntrl0_DDR_CKE           : out   std_logic;
00178     cntrl0_DDR_CS_N          : out   std_logic;
00179     cntrl0_DDR_RAS_N         : out   std_logic;
00180     cntrl0_DDR_CAS_N         : out   std_logic;
00181     cntrl0_DDR_WE_N          : out   std_logic;
00182     cntrl0_DDR_DM            : out   std_logic_vector(3 downto 0);
00183     cntrl0_DDR_CK            : out   std_logic;
00184     cntrl0_DDR_CK_N          : out   std_logic;
00185     cntrl0_DDR_DQ            : inout std_logic_vector(31 downto 0);
00186     cntrl0_DDR_DQS           : inout std_logic_vector(3 downto 0);
00187 -- DDR2
00188     cntrl0_DDR2_A            : out   std_logic_vector(13 downto 0);
00189     cntrl0_DDR2_BA           : out   std_logic_vector(1 downto 0);
00190     cntrl0_DDR2_RAS_N        : out   std_logic;
00191     cntrl0_DDR2_CAS_N        : out   std_logic;
00192     cntrl0_DDR2_WE_N         : out   std_logic;
00193     cntrl0_DDR2_RESET_N      : out   std_logic;
00194     cntrl0_DDR2_CS_N         : out   std_logic;
00195     cntrl0_DDR2_ODT          : out   std_logic;
00196     cntrl0_DDR2_CKE          : out   std_logic;
00197     cntrl0_DDR2_DM           : out   std_logic_vector(7 downto 0);
00198     cntrl0_DDR2_CK           : out   std_logic;
00199     cntrl0_DDR2_CK_N         : out   std_logic;
00200     cntrl0_DDR2_DQ           : inout std_logic_vector(63 downto 0);
00201     cntrl0_DDR2_DQS          : inout std_logic_vector(7 downto 0);
00202     cntrl0_DDR2_DQS_N        : inout std_logic_vector(7 downto 0);
00203 -- EMAC
00204     gmii_rx_clk              : in    std_logic;
00205     gmii_rx_dv               : in    std_logic;
00206     gmii_rx_er               : in    std_logic;
00207     gmii_rxd                 : in    std_logic_vector(0 to 7);
00208     mdio                     : inout std_logic;
00209     mii_tx_clk               : in    std_logic;
00210     gmii_tx_en               : out   std_logic;
00211     gmii_tx_er               : out   std_logic;
00212     gmii_txd                 : out   std_logic_vector(0 to 3);
00213     MDC_0                    : out   std_logic;
00214     phy_rst_n                : out   std_logic;
00215 -- slink
00216     SL_LFF                   : in    std_logic;
00217     SL_LDOWN                 : in    std_logic;
00218     SL_LRL                   : in    std_logic_vector(3 downto 0);
00219     SL_UCLK                  : out   std_logic;
00220     SL_UD                    : out   std_logic_vector(31 downto 0);
00221     SL_URESET                : out   std_logic;
00222     SL_UTEST                 : out   std_logic;
00223     SL_UWEN                  : out   std_logic;
00224     SL_UCTRL                 : out   std_logic;
00225     SL_UDW                   : out   std_logic_vector(1 downto 0);
00226     BUSY                     : out   std_logic;
00227 -- LTP & CTP Interface
00228     ORBIT                    : in    std_logic;
00229     L1A                      : in    std_logic;
00230     TRIGGER_TYPE             : in    std_logic_vector(8 downto 1);
00231     ECR                      : in    std_logic;
00232     BCR                      : in    std_logic;
00233     CTP                      : out   std_logic_vector(9 downto 1);
00234 -- CIBU
00235     POST_LOCK                : in    std_logic;
00236     INJECT_PERM_1            : out   std_logic;
00237     INJECT_PERM_2            : out   std_logic;
00238     BEAM_PERM_1              : out   std_logic;
00239     BEAM_PERM_2              : out   std_logic;
00240 -- DSS
00241     DSS_WARNING_1            : out   std_logic;
00242     DSS_WARNING_2            : out   std_logic;
00243     DSS_ABORT_1              : out   std_logic;
00244     DSS_ABORT_2              : out   std_logic;
00245 -- SATA
00246     RXP_SATA_IN              : in    std_logic_vector (1 downto 0);
00247     RXN_SATA_IN              : in    std_logic_vector (1 downto 0);
00248     TXP_SATA_OUT             : out   std_logic_vector (1 downto 0);
00249     TXN_SATA_OUT             : out   std_logic_vector (1 downto 0);
00250 -- LCD
00251     LCD_E                    : out   std_logic;
00252     LCD_RS                   : out   std_logic;
00253     LCD_RW                   : out   std_logic;
00254     LCD_DIRECTION            : out   std_logic;
00255     LCD_DB                   : inout std_logic_vector(7 downto 0)
00256     );
00257 end bcm_aaa;
00258 
00259 
00260 
00261 
00262 
00263 
00264 architecture bcm_aaa_arc of bcm_aaa is
00265 
00266 --*************************** Signal Declarations *****************************
00267   
00268   signal cs                  : global_states;
00269   signal es                  : err_states;
00270   signal sysclk_i            : std_logic                    := '0';
00271   signal rioclk_1_i          : std_logic                    := '0';
00272   signal rioclk_2_i          : std_logic                    := '0';
00273   signal refclk_p_i          : std_logic                    := '0';
00274   signal refclk_n_i          : std_logic                    := '0';
00275   signal bclk_i              : std_logic                    := '0';
00276   signal bclk2x_p_i          : std_logic                    := '0';
00277   signal bclk2x_n_i          : std_logic                    := '0';
00278   signal bclk4x_p_i          : std_logic                    := '0';
00279   signal bclk4x_n_i          : std_logic                    := '0';
00280   signal emac_clk_i          : std_logic                    := '0';
00281   signal ddrclk_i            : std_logic                    := '0';
00282   signal inttrig_clk_i       : std_logic                    := '0';
00283   signal clkledn             : std_logic                    := '0';
00284   signal clk2_pos            : std_logic                    := '0';
00285   signal clk2_neg            : std_logic                    := '0';
00286   signal sata_clk_i          : std_logic                    := '0';
00287   signal sata_logic_clk_i    : std_logic                    := '0';
00288   signal clk_50_i            : std_logic                    := '0';
00289   signal clk_hz_i            : std_logic                    := '0';
00290   signal trigger_delayed     : std_logic                    := '0';
00291   signal slave_reset         : std_logic                    := '0';
00292   signal res_pc_i            : std_logic                    := '0';
00293   signal res_pc_p            : std_logic                    := '0';
00294   signal res_pc_ii           : std_logic                    := '0';
00295   signal reset_in            : std_logic                    := '0';
00296   signal force_reset         : std_logic                    := '0';
00297   signal force_reset_p       : std_logic                    := '0';
00298   signal force_reset_done    : std_logic                    := '0';
00299   signal all_locked          : std_logic                    := '0';
00300   signal lock_i              : std_logic                    := '0';
00301   signal dump_buf            : std_logic                    := '0';
00302   signal rd_done             : std_logic                    := '0';
00303   signal calib_done          : std_logic                    := '0';
00304   signal cal_rios            : std_logic                    := '0';
00305   signal take_data           : std_logic                    := '0';
00306   signal rios_rdy            : std_logic                    := '0';
00307   signal trigger_i           : std_logic                    := '0';
00308   signal inttrig             : std_logic                    := '0';
00309   signal rioerr_ind          : std_logic                    := '0';
00310   signal rioerr_ind1         : std_logic                    := '0';
00311   signal err_ind             : std_logic                    := '0';
00312   signal send_err            : std_logic                    := '0';
00313   signal trigger_inhibit_n   : std_logic                    := '0';
00314   signal trigger_inhibit_n_i : std_logic                    := '0';
00315   signal sata_ok_i           : std_logic                    := '0';
00316   signal sata_ok_disp        : std_logic                    := '0';
00317   signal trig_pc_i           : std_logic                    := '0';
00318   signal stop_pc_i           : std_logic                    := '0';
00319   signal rd_rdy              : std_logic                    := '0';
00320   signal rd_ovr              : std_logic                    := '0';
00321   signal error_flag          : std_logic                    := '0';
00322   signal inj_perm_i          : std_logic                    := '0';
00323   signal inj_perm_i1         : std_logic                    := '0';
00324   signal inj_perm_i2         : std_logic                    := '0';
00325   signal beam_perm_i         : std_logic                    := '0';
00326   signal beam_perm_i1        : std_logic                    := '0';
00327   signal beam_perm_i2        : std_logic                    := '0';
00328   signal busy_i              : std_logic                    := '0';
00329   signal comm_ok             : std_logic                    := '0';
00330   signal post_lock_i         : std_logic                    := '0';
00331   signal post_mortem         : std_logic                    := '0';
00332   signal pm_i                : std_logic                    := '0';
00333   signal pm_pc_i             : std_logic                    := '0';
00334   signal l1a_i               : std_logic                    := '0';
00335   signal bcr_i               : std_logic                    := '0';
00336   signal ecr_i               : std_logic                    := '0';
00337   signal orbit_i             : std_logic                    := '0';
00338   signal mode_i              : std_logic                    := '0';
00339   signal l1a_disp            : std_logic                    := '0';
00340   signal l1a_disp1           : std_logic                    := '0';
00341   signal gp_err_flag         : std_logic                    := '0';
00342   signal ctp_i               : std_logic_vector(9 downto 1) := (others => '0');
00343   signal main_fsm_st_i       : std_logic_vector(7 downto 0) := (others => '0');
00344   signal cnt                 : std_logic_vector(9 downto 0) := (others => '0');
00345   signal rioerr_type_i       : std_logic_vector(7 downto 0) := (others => '0');
00346   signal error_code_i        : std_logic_vector(7 downto 0) := (others => '0');
00347 
00348   alias clk is refclk_p_i;
00349   alias res is slave_reset;
00350 
00351 --*************************************************************************
00352 --                              main code
00353 --*************************************************************************
00354 begin
00355 
00356   VALID_all <= calib_done;
00357   reset_in  <= RESET or res_pc_i or force_reset_p;
00358 
00359 
00360   sync_reset_in : process(sysclk_i)
00361   begin
00362     if sysclk_i'event and sysclk_i = '1' then
00363       if reset_in = '1' or all_locked = '0' then
00364         slave_reset <= '1';
00365       else
00366         slave_reset <= '0';
00367       end if;
00368     end if;
00369   end process sync_reset_in;
00370 
00371 
00372   reset_force : process (clk_hz_i, slave_reset)
00373     variable cnt : integer range 0 to 7 := 0;
00374   begin  -- process reset_force
00375     if slave_reset = '1' then           -- asynchronous reset (active high)
00376       force_reset <= '0';
00377 --      force_reset_done <= '0';
00378       cnt         := 0;
00379     elsif clk_hz_i'event and clk_hz_i = '1' then  -- rising clock edge
00380       if force_reset_done = '0' then
00381         cnt := cnt + 1;
00382         if cnt = 1 then
00383           force_reset      <= '1';
00384           force_reset_done <= '1';
00385         end if;
00386       else
00387         force_reset <= '0';
00388         cnt         := cnt;
00389       end if;
00390     end if;
00391   end process reset_force;
00392 
00393 
00394   rd_rdy_sync : edge
00395     port map (
00396       CLK   => bclk_i,
00397       A     => force_reset,
00398       PULSE => force_reset_p
00399       );
00400 
00401 
00402 --*************************************************************************************
00403 --*                                     main FSM
00404 --*************************************************************************************
00405 
00406 
00407 
00408 
00409 
00410 
00411   main_fsm : process(clk)
00412   begin
00413     if clk'event and clk = '1' then
00414       if res = '1' then
00415         cs <= g_reset;
00416       else
00417         case cs is
00418 
00419           when g_reset =>
00420             cs <= g_idle;
00421             
00422           when g_idle =>                --* wait a bit after reset
00423             cnt <= cnt + 1;
00424             if cnt = "0000011111" then
00425               if kIgnoreRioCal = true then
00426                 cs <= g_capture;
00427               else
00428                 cs <= g_waitriostartup;
00429               end if;
00430               cnt <= (others => '0');
00431             else
00432               cs <= g_idle;
00433             end if;
00434 
00435           when g_waitriostartup =>      --* wait for RIOs to lock
00436             if rios_rdy = '1' then
00437               cs <= g_calib;
00438             else
00439               cs <= g_waitriostartup;
00440             end if;
00441             
00442           when g_calib =>  --* wait for RIOs to get ready for valid data taking
00443             if calib_done = '1' then    --and sata_ok_i = '1' then
00444               cs <= g_capture;
00445             else
00446               cs <= g_calib;
00447             end if;
00448             
00449           when g_capture =>
00450             if err_ind = '1' then
00451               cs <= g_error;
00452             elsif pm_i = '1' then
00453               cs <= g_freeze;
00454             elsif trig_pc_i = '1' then
00455               cs <= g_read;
00456             else
00457               cs <= g_capture;
00458             end if;
00459 
00460           when g_freeze =>
00461             if err_ind = '1' then
00462               cs <= g_error;
00463             elsif trig_pc_i = '1' then
00464               cs <= g_read;
00465             else
00466               cs <= g_freeze;
00467             end if;
00468             
00469           when g_read =>                --* dump buffers to PC
00470             if err_ind = '1' then
00471               cs <= g_error;
00472             elsif rd_done = '1' or stop_pc_i = '1' then
00473               cs <= g_armed;
00474             else
00475               cs <= g_read;
00476             end if;
00477 
00478           when g_armed =>
00479             if err_ind = '1' then
00480               cs <= g_error;
00481             else
00482               cs <= g_capture;
00483             end if;
00484 
00485           when g_error =>
00486             cs <= g_error;
00487             
00488           when others =>
00489             cs <= g_error;
00490             
00491         end case;
00492       end if;
00493     end if;
00494   end process main_fsm;
00495 
00496 --*************************************************************************************
00497 --*                             decode main FSM outputs
00498 --*************************************************************************************
00499 
00500   SOS_LED <= take_data;
00501 
00502 
00503 
00504 
00505   main_fsm_out : process(clk)
00506   begin
00507     if clk'event and clk = '1' then
00508       if res = '1' then
00509         cal_rios     <= '0';
00510         take_data    <= '0';
00511         dump_buf     <= '0';
00512         rd_rdy       <= '0';
00513         rd_ovr       <= '0';
00514         send_err     <= '0';
00515         error_code_i <= (others => '0');
00516       else
00517         cal_rios  <= '0';
00518         take_data <= '0';
00519         dump_buf  <= '0';
00520         rd_rdy    <= '0';
00521         rd_ovr    <= '0';
00522         send_err  <= '0';
00523 
00524         case cs is
00525 
00526           when g_reset =>
00527             null;
00528           when g_waitriostartup =>
00529             null;
00530           when g_calib =>
00531             cal_rios <= '1';
00532           when g_idle =>
00533             null;
00534           when g_capture =>
00535             take_data <= '1';
00536           when g_freeze =>
00537             rd_rdy    <= '1';
00538             take_data <= '0';
00539             dump_buf  <= '0';
00540           when g_read =>
00541             dump_buf <= '1';
00542           when g_armed =>
00543             rd_ovr   <= '1';
00544             dump_buf <= '0';
00545           when g_error =>
00546             if kErr_Msg_En = true then  --* mask sending of err msg
00547               send_err <= '1';
00548             end if;
00549             --* decode different errors
00550             if rioerr_ind1 = '1' then
00551               error_code_i <= "00000001";
00552             end if;
00553           when others =>
00554             null;
00555         end case;
00556       end if;
00557     end if;
00558   end process main_fsm_out;
00559 
00560 --*************************************************************************************
00561 --*                                decode main FSM states
00562 --*************************************************************************************
00563 
00564 
00565 
00566 
00567   main_fsm_states : process (clk)
00568   begin  -- process main_fsm_states
00569     if clk'event and clk = '1' then     -- rising clock edge
00570       case cs is
00571         when g_waitriostartup => main_fsm_st_i <= "00000001";
00572         when g_calib          => main_fsm_st_i <= "00000011";
00573         when g_idle           => main_fsm_st_i <= "00000010";
00574         when g_capture        => main_fsm_st_i <= "00000110";
00575         when g_reset          => main_fsm_st_i <= "00000111";
00576         when g_read           => main_fsm_st_i <= "00000101";
00577         when g_error          => main_fsm_st_i <= "00000100";
00578         when g_freeze         => main_fsm_st_i <= "00001100";
00579         when g_armed          => main_fsm_st_i <= "00001101";
00580         when others           => main_fsm_st_i <= (others => '0');
00581       end case;
00582     end if;
00583   end process main_fsm_states;
00584 
00585 --*************************************************************************************
00586 --*                                     emergency FSM
00587 --*************************************************************************************
00588 
00589 
00590 
00591 
00592 
00593 
00594 
00595   emergency_fsm : process (sysclk_i, RESET)
00596   begin  -- process emergency_fsm
00597     if RESET = '1' then                 -- asynchronous reset (active high)
00598       es <= err_no;
00599     elsif sysclk_i'event and sysclk_i = '1' then  -- rising clock edge
00600       case es is
00601         when err_no =>
00602           if CLK_DET = '0' then
00603             es <= err_yes;
00604           else
00605             es <= err_no;
00606           end if;
00607         when err_yes =>
00608           null;
00609         when others =>
00610           es <= err_yes;
00611       end case;
00612     end if;
00613   end process emergency_fsm;
00614 
00615 --************************** Component Instantiations ***************************
00616 
00617 
00618   clock_module : clocks
00619     port map
00620     (
00621       RESET                    => '0',
00622       SYSCLK                   => SYSCLK,
00623       REFCLK                   => '0',
00624       BCLK4X                   => '0',
00625       UPPER_MGTCLK_PAD_P_IN_EX => UPPER_MGTCLK_PAD_P_IN_EX,
00626       UPPER_MGTCLK_PAD_N_IN_EX => UPPER_MGTCLK_PAD_N_IN_EX,
00627       SYSCLK_INT               => sysclk_i,
00628       REFCLK_P                 => refclk_p_i,
00629       REFCLK_N                 => open,
00630       DDRCLK                   => ddrclk_i,
00631       BCLK                     => bclk_i,
00632       BCLK2X_P                 => bclk2x_p_i,
00633       BCLK2X_N                 => open,
00634       BCLK4X_P                 => bclk4x_p_i,
00635       BCLK4X_N                 => open,
00636       RIOCLK_1                 => rioclk_1_i,
00637       RIOCLK_2                 => open,
00638       EMAC_CLK                 => emac_clk_i,
00639       SATA_CLK                 => sata_clk_i,
00640       SATA_LOGIC_CLK           => sata_logic_clk_i,
00641       CLK_50MHz_OUT            => clk_50_i,
00642       INTTRIG_CLK              => inttrig_clk_i,
00643       CLK_HZ                   => clk_hz_i,
00644       XTAL_SEL                 => XTAL_SEL,
00645       CLK_DET                  => CLK_DET,
00646       LOCK                     => all_locked 
00647       );
00648 
00649   trigger_inhibit_n <= take_data and trigger_inhibit_n_i;
00650   trigger_i         <= trig_pc_i;
00651 
00652 
00653   post_lock_sync : edge
00654     port map (
00655       CLK   => refclk_p_i,
00656       A     => POST_LOCK ,
00657       PULSE => post_lock_i
00658       );
00659 
00660   post_mortem <= post_lock_i or pm_pc_i;
00661 
00662 
00663   pm_delay : pmdelay
00664     generic map(
00665       LAYOFF => 100 )
00666     port map
00667     (
00668       CLK    => refclk_p_i ,
00669       RES     => res ,
00670       PM_IN   => post_mortem,
00671       ORBIT  => orbit_i,
00672       PM_OUT => pm_i
00673       );
00674 
00675 
00676   main : rio2mem
00677     port map
00678     (
00679       BCLK                => bclk_i,
00680       RIOCLK_1            => rioclk_1_i,
00681       RIOCLK_2            => '0',
00682       BCLK2X_P            => bclk2x_p_i ,
00683       BCLK2X_N            => '0',
00684       BCLK4X_P            => bclk4x_p_i,
00685       BCLK4X_N            => '0',
00686       REFCLK_P            => refclk_p_i,
00687       REFCLK_N            => '0',
00688       EMAC_CLK            => emac_clk_i,
00689       DDRCLK              => ddrclk_i,
00690       SATA_REF_CLK        => sata_clk_i,
00691       SATA_LOGIC_CLK      => sata_logic_clk_i,
00692       CLK_50              => clk_50_i,
00693       CLK_HZ              => clk_hz_i,
00694       XT_CLK_DET          => CLK_DET,
00695       MODE                => mode_i,
00696       GP_ERR_FLAG         => gp_err_flag,
00697       RESET               => slave_reset,
00698       RES_PC              => res_pc_ii,
00699       TRIG_PC             => trig_pc_i,
00700       STOP_PC             => stop_pc_i,
00701       FORCE_PM            => pm_pc_i,
00702       CALIBRATE_RIOS      => cal_rios,
00703       CHECK               => open,
00704       RIOS_READY          => rios_rdy,
00705       LOCK_OUT            => lock_i,
00706       MAC_LOCK            => open,
00707       CAL_DONE            => calib_done,
00708       SEND_ARP_ANN        => '0',
00709       READ_OUT            => dump_buf,
00710       CAPTURE             => take_data,
00711       GOTO_RD             => open,
00712       READ_DONE           => rd_done,
00713       READ_READY          => rd_rdy,
00714       READ_OVER           => rd_ovr,
00715       TRIGGER_INHIBIT_N   => trigger_inhibit_n_i,
00716       MAIN_FSM_ST         => main_fsm_st_i,
00717       RXP_SATA_IN         => RXP_SATA_IN,
00718       RXN_SATA_IN         => RXN_SATA_IN,
00719       TXP_SATA_OUT        => TXP_SATA_OUT,
00720       TXN_SATA_OUT        => TXN_SATA_OUT,
00721       SATA_OK             => sata_ok_i,
00722       RXN_C_IE            => RXN_C_IE,
00723       RXP_C_IE            => RXP_C_IE,
00724       RXN_C_AH            => RXN_C_AH,
00725       RXP_C_AH            => RXP_C_AH,
00726       RXN_A_WM            => RXN_A_WM,
00727       RXP_A_WM            => RXP_A_WM,
00728       RXN_A_HH            => RXN_A_HH,
00729       RXP_A_HH            => RXP_A_HH,
00730       TXN_C_IE            => TXN_C_IE,
00731       TXP_C_IE            => TXP_C_IE,
00732       TXN_C_AH            => TXN_C_AH,
00733       TXP_C_AH            => TXP_C_AH,
00734       TXN_A_WM            => TXN_A_WM,
00735       TXP_A_WM            => TXP_A_WM,
00736       TXN_A_HH            => TXN_A_HH,
00737       TXP_A_HH            => TXP_A_HH,
00738       MASK_IRENA          => MASK_IRENA,
00739       MASK_EWA            => MASK_EWA,
00740       MASK_ANDREJ         => MASK_ANDREJ,
00741       MASK_HEINZ          => MASK_HEINZ,
00742       MASK_MARKO          => MASK_MARKO,
00743       MASK_WILLIAM        => MASK_WILLIAM,
00744       MASK_HARRIS         => MASK_HARRIS,
00745       MASK_HELMUT         => MASK_HELMUT,
00746       OR_CH1              => open,
00747       OR_CH2              => open,
00748       cntrl0_DDR_DQ       => cntrl0_DDR_DQ,
00749       cntrl0_DDR_DQS      => cntrl0_DDR_DQS,
00750       cntrl0_DDR_A        => cntrl0_DDR_A,
00751       cntrl0_DDR_BA       => cntrl0_DDR_BA,
00752       cntrl0_DDR_CKE      => cntrl0_DDR_CKE,
00753       cntrl0_DDR_CS_N     => cntrl0_DDR_CS_N,
00754       cntrl0_DDR_RAS_N    => cntrl0_DDR_RAS_N,
00755       cntrl0_DDR_CAS_N    => cntrl0_DDR_CAS_N,
00756       cntrl0_DDR_WE_N     => cntrl0_DDR_WE_N,
00757       cntrl0_DDR_DM       => cntrl0_DDR_DM,
00758       cntrl0_DDR_CK       => cntrl0_DDR_CK,
00759       cntrl0_DDR_CK_N     => cntrl0_DDR_CK_N,
00760       cntrl0_DDR2_DQ      => cntrl0_DDR2_DQ,
00761       cntrl0_DDR2_DQS     => cntrl0_DDR2_DQS,
00762       cntrl0_DDR2_DQS_N   => cntrl0_DDR2_DQS_N,
00763       cntrl0_DDR2_A       => cntrl0_DDR2_A,
00764       cntrl0_DDR2_BA      => cntrl0_DDR2_BA,
00765       cntrl0_DDR2_RAS_N   => cntrl0_DDR2_RAS_N,
00766       cntrl0_DDR2_CAS_N   => cntrl0_DDR2_CAS_N,
00767       cntrl0_DDR2_WE_N    => cntrl0_DDR2_WE_N,
00768       cntrl0_DDR2_RESET_N => cntrl0_DDR2_RESET_N,
00769       cntrl0_DDR2_CS_N    => cntrl0_DDR2_CS_N,
00770       cntrl0_DDR2_ODT     => cntrl0_DDR2_ODT,
00771       cntrl0_DDR2_CKE     => cntrl0_DDR2_CKE,
00772       cntrl0_DDR2_DM      => cntrl0_DDR2_DM,
00773       cntrl0_DDR2_CK      => cntrl0_DDR2_CK,
00774       cntrl0_DDR2_CK_N    => cntrl0_DDR2_CK_N,
00775       gmii_rx_clk         => GMII_RX_CLK,
00776       gmii_rx_dv          => GMII_RX_DV,
00777       gmii_rx_er          => GMII_RX_ER,
00778       gmii_rxd            => GMII_RXD,
00779       mii_tx_clk          => MII_TX_CLK,
00780       gmii_tx_en          => GMII_TX_EN,
00781       gmii_tx_er          => GMII_TX_ER,
00782       gmii_txd            => GMII_TXD,
00783       MDC_0               => MDC_0,
00784       mdio                => MDIO,
00785       TRIG_EXT            => trigger_i,
00786       phy_rst_n           => PHY_RST_N,
00787       SL_LFF              => SL_LFF,
00788       SL_LDOWN            => SL_LDOWN,
00789       SL_LRL              => "0000",
00790       SL_UCLK             => SL_UCLK,
00791       SL_UD               => SL_UD,
00792       SL_URESET           => SL_URESET,
00793       SL_UTEST            => SL_UTEST,
00794       SL_UWEN             => SL_UWEN,
00795       SL_UCTRL            => SL_UCTRL,
00796       SL_UDW              => SL_UDW,
00797       BUSY                => busy_i,
00798       ORBIT               => orbit_i,
00799       L1A                 => l1a_i,
00800       ECR                 => ecr_i,
00801       BCR                 => bcr_i,
00802       TRIGGER_TYPE        => TRIGGER_TYPE,
00803       CTP                 => ctp_i,
00804       INJECT_PERM_1       => inj_perm_i1,
00805       INJECT_PERM_2       => inj_perm_i2,
00806       BEAM_PERM_1         => beam_perm_i1,
00807       BEAM_PERM_2         => beam_perm_i2,
00808       DSS_ABORT_1         => DSS_ABORT_1,
00809       DSS_ABORT_2         => DSS_ABORT_2,
00810       DSS_WARNING_1       => DSS_WARNING_1,
00811       DSS_WARNING_2       => DSS_WARNING_2,
00812       L1A_DISP            => l1a_disp,
00813       RIOERR              => rioerr_ind,
00814       RIOERR_TYPE         => rioerr_type_i,
00815       SEND_ERR_MSG        => send_err,
00816       ERROR_CODE          => error_code_i
00817       );
00818 
00819   -- map signals to pins & get intermediates for status LEDs
00820   INJECT_PERM_1 <= inj_perm_i1;
00821   INJECT_PERM_2 <= inj_perm_i2;
00822   inj_perm_i    <= inj_perm_i1 and inj_perm_i2;
00823   BEAM_PERM_1   <= beam_perm_i1;
00824   BEAM_PERM_2   <= beam_perm_i2;
00825   beam_perm_i   <= beam_perm_i1 and beam_perm_i2;
00826   -- invert NIM IOs
00827   BUSY          <= not busy_i;
00828   l1a_i         <= not L1A;
00829   ecr_i         <= not ECR;
00830   bcr_i         <= not BCR;
00831   orbit_i       <= not ORBIT;
00832   CTP           <= not ctp_i;
00833 
00834   rem_res_pulse : edge
00835     port map (
00836       CLK   => sysclk_i ,
00837       A     => res_pc_ii ,
00838       PULSE => res_pc_p
00839       );
00840 
00841   rem_res_ext : extend_test
00842     generic map (
00843       LEN => 30 )
00844     port map
00845     (
00846       CLK  => sysclk_i ,
00847       RES  => '0' ,
00848       ENDM => open,
00849       A    => res_pc_p ,
00850       Y    => res_pc_i 
00851       );
00852 
00853   err_ind     <= rioerr_ind;
00854   rioerr_ind1 <= rioerr_ind when rising_edge(clk);
00855 
00856 --*************************************************************************************
00857 --*                              LCD or Status LEDS
00858 --*          just cause everyone needs some useless but cute crap :-)
00859 --*************************************************************************************
00860 
00861 
00862   LCD_use : if kInclLcd = true generate
00863 
00864 
00865     LCD_all : LCD
00866       port map(
00867         LCDCLK        => sysclk_i,
00868         TAKE          => take_data,
00869         GIVE          => dump_buf,
00870         RES           => res,
00871         LCD_DIRECTION => LCD_DIRECTION,
00872         LCD_RS        => LCD_RS,
00873         LCD_RW        => LCD_RW,
00874         LCD_E         => LCD_E,
00875         LCD_DB        => LCD_DB
00876         );
00877 
00878   end generate LCD_use;
00879 
00880 
00881   LCD_no : if kInclLcd = false generate
00882 
00883 
00884     l1a_display_extend : extend_test
00885       generic map (
00886         LEN => 60 )
00887       port map
00888       (
00889         CLK  => bclk_i,
00890         RES   => slave_reset,
00891         ENDM  => open ,
00892         A     => l1a_i ,
00893         Y    => l1a_disp1 
00894         );
00895 
00896     clkledn <= not inttrig_clk_i;
00897 
00898     pos_edge_10k : edge
00899       port map (
00900         CLK   => bclk_i,
00901         A     => inttrig_clk_i,
00902         PULSE => clk2_pos
00903         );
00904 
00905     neg_edge_10k : edge
00906       port map (
00907         CLK   => bclk_i,
00908         A     => clkledn ,
00909         PULSE => clk2_neg
00910         );
00911 
00912     l1a_disp <= '1' when l1a_disp1 = '1' else
00913                 '0' when (slave_reset or clk2_pos or clk2_neg) = '1';
00914     
00915     LCD_E         <= '0';
00916     LCD_RS        <= '0';
00917     LCD_RW        <= '0';
00918     LCD_DIRECTION <= '1';               -- set to 1 to write to LEDs
00919     error_flag    <= gp_err_flag or (not all_locked);
00920     sata_ok_disp  <= '0' when slave_reset = '1' else sata_ok_i;
00921 
00922     --* LEDs
00923     LCD_DB(7) <= error_flag;
00924     LCD_DB(6) <= mode_i;
00925     LCD_DB(5) <= beam_perm_i;
00926     LCD_DB(4) <= inj_perm_i;
00927     LCD_DB(3) <= busy_i;
00928     LCD_DB(2) <= l1a_disp;
00929     LCD_DB(1) <= comm_ok;
00930     LCD_DB(0) <= sata_ok_disp;
00931   end generate LCD_no;
00932   
00933 end bcm_aaa_arc;