statistics.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/coin/statistics.vhd,v $
--*  $Revision: 1.2.2.3 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:43 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;





entity statistics is
  
  generic (
    SERIES_LENGTH : integer := 4096);

  port (
    CLK : in  std_logic;
    RES : in  std_logic;
    VAL : in  std_logic_vector(15 downto 0);
    MNM : out std_logic_vector(15 downto 0);
    MAX : out std_logic_vector(15 downto 0);
    AVG : out std_logic_vector(15 downto 0)
    );

end statistics;





architecture statistics_arc of statistics is


  component division
    generic (
      DIVISOR : integer);
    port (
      CLK : in  std_logic;
      RES : in  std_logic;
      A   : in  unsigned(15 downto 0);
      C   : out unsigned(15 downto 0));
  end component;


  function safe_div (
    A : integer)
    return integer is
    variable Ai  : integer;
    variable ret : integer := 2;
  begin  -- safe_div
    Ai := A;
    while 0 < 1 loop
      if Ai < 2 then
        ret := 2;
        exit;
      else
        if Ai mod 2 /= 0 then
          Ai := Ai - 1;
        else
          ret := Ai;
          exit;
        end if;
      end if;
    end loop;
    return ret;
  end safe_div;


  constant c_len : integer := safe_div(SERIES_LENGTH);

  signal ser_end     : std_logic             := '0';
  signal res_int     : std_logic             := '0';
  signal minimum_reg : unsigned(15 downto 0) := (others => '0');
  signal maximum_reg : unsigned(15 downto 0) := (others => '0');
  signal average_reg : unsigned(15 downto 0) := (others => '0');
  signal accu_reg    : unsigned(15 downto 0) := (others => '0');
  signal avg_in      : unsigned(15 downto 0) := (others => '0');
  signal avg_out     : unsigned(15 downto 0) := (others => '0');

begin  -- statistics_arc

  res_int <= RES or ser_end;


  series_cnt : process (CLK)
    variable cnt : integer := 0;
  begin  -- process series_cnt
    if CLK'event and CLK = '1' then     -- rising clock edge
      if RES = '1' then
        cnt     := 0;
        ser_end <= '0';
      else
        ser_end <= '0';
        cnt     := cnt + 1;
        if cnt = c_len then
          ser_end <= '1';
          cnt     := 0;
        end if;
      end if;
    end if;
  end process series_cnt;


  minimum_cal : process (CLK)
  begin  -- process minimum
    if CLK'event and CLK = '1' then     -- rising clock edge
      if res_int = '1' then
        minimum_reg <= unsigned(VAL);
      elsif unsigned(VAL) <= minimum_reg then
        minimum_reg <= unsigned(VAL);
      else
        minimum_reg <= minimum_reg;
      end if;
    end if;
  end process minimum_cal;

  MNM <= std_logic_vector(minimum_reg);


  maximum_cal : process (CLK)
  begin  -- process minimum
    if CLK'event and CLK = '1' then     -- rising clock edge
      if res_int = '1' then
        maximum_reg <= unsigned(VAL);
      elsif unsigned(VAL) > maximum_reg then
        maximum_reg <= unsigned(VAL);
      else
        maximum_reg <= maximum_reg;
      end if;
    end if;
  end process maximum_cal;

  MAX <= std_logic_vector(maximum_reg);

  avg_acc : process (CLK)
  begin  -- process avg_acc
    if CLK'event and CLK = '1' then     -- rising clock edge
      if res_int = '1' then
        accu_reg <= (others => '0');
        if ser_end = '1' then
          average_reg <= accu_reg + unsigned(VAL);
        else
          average_reg <= (others => '0');
        end if;
      else
        accu_reg <= accu_reg + unsigned(VAL);
      end if;
    end if;
  end process avg_acc;

  avg_in <= average_reg;


  average_cal : division
    generic map (
      DIVISOR => c_len)
    port map (
      CLK => CLK ,
      RES => RES ,
      A   => avg_in ,
      C   => avg_out 
      );

  AVG <= std_logic_vector(avg_out);

end statistics_arc;

---

Author: M.Niegl

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