division.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/coin/division.vhd,v $
--*  $Revision: 1.3.2.3 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:42 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;





entity division is
  
  generic (
    DIVISOR : integer := 4096
    );
  port (
    CLK : in  std_logic;
    RES : in  std_logic;
    A   : in  unsigned(15 downto 0);
    C   : out unsigned(15 downto 0)
    );

end division;





architecture division_arc of division is


  function safe_div (
    A : integer)
    return integer is
    variable Ai  : integer;
    variable ret : integer := 2;
  begin  -- safe_div
    Ai := A;
    while 0 < 1 loop
      if Ai < 2 then
        ret := 2;
        exit;
      else
        if Ai mod 2 /= 0 then
          Ai := Ai - 1;
        else
          ret := Ai;
          exit;
        end if;
      end if;
    end loop;
    return ret;
  end safe_div;


  constant c_divisor : integer := safe_div(DIVISOR);

begin  -- division_arc


  div : process (CLK)
  begin  -- process div
    if CLK'event and CLK = '1' then     -- rising clock edge
      if RES = '1' then
        C <= (others => '0');
      else
        C <= A / c_divisor;
      end if;
    end if;
  end process div;

end division_arc;

---

Author: M.Niegl

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