ddr2_usr_be.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--* *
--* $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr2/ddr2_usr_be.vhd,v $ *
--* $Revision: 1.13.2.4 $ *
--* $Name: dev $ *
--* $Author: mniegl $ *
--* $Date: 2008/11/03 17:57:45 $ *


--* *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

library unisim;

use unisim.vcomponents.all;





entity ddr2_usr_be is
  port(
    cntrl0_DDR2_DQ      : inout std_logic_vector(63 downto 0);
    cntrl0_DDR2_DQS     : inout std_logic_vector(7 downto 0);
    cntrl0_DDR2_DQS_N   : inout std_logic_vector(7 downto 0);
    cntrl0_DDR2_A       : out   std_logic_vector(13 downto 0);
    cntrl0_DDR2_BA      : out   std_logic_vector(1 downto 0);
    cntrl0_DDR2_RAS_N   : out   std_logic;
    cntrl0_DDR2_CAS_N   : out   std_logic;
    cntrl0_DDR2_WE_N    : out   std_logic;
    cntrl0_DDR2_RESET_N : out   std_logic;
    cntrl0_DDR2_CS_N    : out   std_logic;
    cntrl0_DDR2_ODT     : out   std_logic;
    cntrl0_DDR2_CKE     : out   std_logic;
    cntrl0_DDR2_DM      : out   std_logic_vector(7 downto 0);
    cntrl0_DDR2_CK      : out   std_logic;
    cntrl0_DDR2_CK_N    : out   std_logic;
    COMP_OUT1           : out   std_logic;
    COMP_OUT2           : out   std_logic;
    LED_CONTR           : out   std_logic;
    LED_R               : out   std_logic;
    VALID_OUT           : out   std_logic;
    SYSCLK              : in    std_logic;
    CLK_SLOW            : in    std_logic;
    R_W                 : in    std_logic;
    FETCH               : out   std_logic;
    RESET_IN            : in    std_logic;
    ADDR_RES            : in    std_logic;
    ADDR_OVR            : out   std_logic;
    DATA_IN             : in    std_logic_vector(127 downto 0);
    EN                  : in    std_logic;
    RDBURST_END         : out   std_logic;
    DATA_OUT            : out   std_logic_vector(127 downto 0)
    );
end ddr2_usr_be;




architecture ddr2_usr_be_arc of ddr2_usr_be is

--*************************** Signal Declarations *****************************
  signal clk_tb      : std_logic                      := '0';
  signal data_full   : std_logic                      := '0';
  signal addr_full   : std_logic                      := '0';
  signal data_en     : std_logic                      := '0';
  signal data_en_i   : std_logic                      := '0';
  signal addr_en     : std_logic                      := '0';
  signal addr_en_ram : std_logic                      := '0';
  signal nop_en      : std_logic                      := '0';
  signal valid       : std_logic                      := '0';
  signal reset       : std_logic                      := '0';
  signal res_out     : std_logic                      := '0';
  signal res_in      : std_logic                      := '0';
  signal CS          : std_logic                      := '0';
  signal AP          : std_logic                      := '0';
  signal addr_ovr_i  : std_logic                      := '0';
  signal mask        : std_logic_vector(15 downto 0)  := (others => '0');
  signal write_data  : std_logic_vector(127 downto 0) := (others => '0');
  signal read_data1  : std_logic_vector(127 downto 0) := (others => '0');
  signal addr        : std_logic_vector(35 downto 0)  := (others => '0');
  signal addr_ram    : std_logic_vector(35 downto 0)  := (others => '0');
  signal cmd         : std_logic_vector(2 downto 0)   := (others => '0');
  signal nop_cnt     : std_logic_vector(2 downto 0)   := (others => '0');
  signal burst_cnt   : std_logic_vector(1 downto 0)   := (others => '0');
  signal bank_sel    : std_logic_vector(1 downto 0)   := (others => '0');
  signal row_sel     : std_logic_vector(12 downto 0)  := (others => '0');
  signal column_sel  : std_logic_vector(6 downto 0)   := (others => '0');
  signal block_start : std_logic_vector(2 downto 0)   := (others => '0');

--************************** Component Declarations ***************************

  component ddr2_mem
    port(
      SYS_CLK_P                 : in    std_logic;
      SYS_CLK_N                 : in    std_logic;
      CLK200_P                  : in    std_logic;
      CLK200_N                  : in    std_logic;
      SYS_RESET_IN              : in    std_logic;
      cntrl0_APP_WDF_WREN       : in    std_logic;
      cntrl0_APP_AF_WREN        : in    std_logic;
      cntrl0_APP_AF_ADDR        : in    std_logic_vector(35 downto 0);
      cntrl0_APP_WDF_DATA       : in    std_logic_vector(127 downto 0);
      cntrl0_APP_MASK_DATA      : in    std_logic_vector(15 downto 0);
      cntrl0_DDR2_DQ            : inout std_logic_vector(63 downto 0);
      cntrl0_DDR2_DQS           : inout std_logic_vector(7 downto 0);
      cntrl0_DDR2_DQS_N         : inout std_logic_vector(7 downto 0);
      cntrl0_DDR2_A             : out   std_logic_vector(13 downto 0);
      cntrl0_DDR2_BA            : out   std_logic_vector(1 downto 0);
      cntrl0_DDR2_RAS_N         : out   std_logic;
      cntrl0_DDR2_CAS_N         : out   std_logic;
      cntrl0_DDR2_WE_N          : out   std_logic;
      cntrl0_DDR2_RESET_N       : out   std_logic;
      cntrl0_DDR2_CS_N          : out   std_logic;
      cntrl0_DDR2_ODT           : out   std_logic;
      cntrl0_DDR2_CKE           : out   std_logic;
      cntrl0_DDR2_DM            : out   std_logic_vector(7 downto 0);
      cntrl0_CLK_TB             : out   std_logic;
      cntrl0_RESET_TB           : out   std_logic;
      cntrl0_WDF_ALMOST_FULL    : out   std_logic;
      cntrl0_AF_ALMOST_FULL     : out   std_logic;
      cntrl0_READ_DATA_VALID    : out   std_logic;
      cntrl0_BURST_LENGTH       : out   std_logic_vector(2 downto 0);
      cntrl0_READ_DATA_FIFO_OUT : out   std_logic_vector(127 downto 0);
      cntrl0_DDR2_CK            : out   std_logic;
      cntrl0_DDR2_CK_N          : out   std_logic;
      LOCK_IN                   : in    std_logic
      );
  end component;


  component edge
    port(
      CLK   : in  std_logic;
      A     : in  std_logic;
      PULSE : out std_logic
      );
  end component;


  component extend_test
    generic (
      LEN : integer range 0 to 63 := 2
      );
    port(
      CLK  : in  std_logic;
      RES  : in  std_logic;
      A    : in  std_logic;
      ENDM : out std_logic;
      Y    : out std_logic
      );
  end component;

--*****************************************************************************
-- main code
--*****************************************************************************
begin

  LED_R       <= '0';
  LED_CONTR   <= '0';
  COMP_OUT1   <= '0';
  COMP_OUT2   <= '0';
  mask        <= (others => '0');
  CS          <= '0';
  AP          <= '0';
  block_start <= "000";

  addr <= '0' & cmd & "0000" & CS & bank_sel & '0' & row_sel & AP & column_sel & block_start;
  cmd  <= "101" when R_W = '1' else     -- read command
          "100";                        -- write command
  addr_ovr_i <= '0' when RESET_IN = '1' else
                '1' when bank_sel = "11" and row_sel = "1111111111111" and column_sel = "1111111" else
                '0';
  addr_ram   <= addr        when rising_edge(clk_tb);
  addr_en    <= addr_en_ram when rising_edge(clk_tb);
  VALID_OUT  <= valid       when rising_edge(clk_tb);
  write_data <= DATA_IN     when rising_edge(clk_tb);
  res_in     <= not RESET_IN;
  FETCH      <= data_en_i;


  reset_ext : extend_test
    generic map (LEN => 20)
    port map(
      CLK  => CLK_SLOW ,
      RES  => RESET_IN ,
      ENDM => open,
      A    => res_out ,
      Y    => reset 
      );


  pulse_ovr : edge
    port map (
      CLK   => clk_tb,
      A     => addr_ovr_i,
      PULSE => ADDR_OVR
      );


  control_data_enable : process(clk_tb)
  begin
    if clk_tb'event and clk_tb = '1' then
      data_en <= data_en_i;
      if reset = '1' then
        data_en_i <= '0';
      else
        if R_W = '0' and data_full = '0' and nop_en = '0' and EN = '1' then
          --if R_W = '0' and stop_write = '0' and nop_en = '0' then
          data_en_i <= '1';
        else
          data_en_i <= '0';
        end if;
      end if;
    end if;
  end process;


  RDBURST_END <= nop_en;


  addr_gen : process(clk_tb)
  begin
    if clk_tb'event and clk_tb = '1' then

      if (reset or ADDR_RES) = '1' then
        column_sel  <= (others => '0');
        bank_sel    <= (others => '0');
        row_sel     <= (others => '0');
        burst_cnt   <= "00";
        nop_cnt     <= (others => '0');
        addr_en_ram <= '0';
        nop_en      <= '0';

      elsif addr_full = '0' and EN = '1' then
-- elsif stop_write = '0' then

        if R_W = '0' and data_full = '0' then  -- 7+1 write burst structure

          burst_cnt <= burst_cnt + 1;
          --addr_en <= '1';
          --nop_en <= '0';

          if burst_cnt = "11" then
            if nop_en = '1' then
              addr_en_ram <= '0';
            else
              addr_en_ram <= '1';
            end if;
            nop_cnt <= nop_cnt + 1;
          else
            addr_en_ram <= '0';
            nop_cnt     <= nop_cnt;
          end if;

          if burst_cnt = "10" then
            if nop_cnt = "111" then
              nop_en     <= '1';
              bank_sel   <= bank_sel;
              column_sel <= column_sel;
              row_sel    <= row_sel;
            else
              nop_en <= '0';
            end if;
          end if;
          if nop_en = '0' then
            if burst_cnt = "11" then
              column_sel <= column_sel + 1;
              if column_sel = "1111111" then
                bank_sel   <= bank_sel + 1;
                column_sel <= (others => '0');
                if bank_sel = "11" then
                  row_sel  <= row_sel + 1;
                  bank_sel <= "00";

                  if row_sel = "1111111111111" then
                    nop_cnt <= (others => '0');
                    nop_en  <= '0';
                  else
                  end if;

                else
                  row_sel <= row_sel;
                end if;
              else
                bank_sel <= bank_sel;
              end if;
            else
              column_sel <= column_sel;
            end if;
          end if;

        else                            -- 1+1 read structure

          burst_cnt <= burst_cnt + 1;

          if burst_cnt = "11" then
            if nop_en = '1' then
              addr_en_ram <= '0';
            else
              addr_en_ram <= '1';
            end if;
            nop_en <= not nop_en;
          else
            addr_en_ram <= '0';
            nop_cnt     <= nop_cnt;
          end if;

          if nop_en = '0' then
            if burst_cnt = "11" then
              column_sel <= column_sel + 1;
              if column_sel = "1111111" then
                bank_sel   <= bank_sel + 1;
                column_sel <= (others => '0');
                if bank_sel = "11" then
                  row_sel  <= row_sel + 1;
                  bank_sel <= "00";

                  if row_sel = "1111111111111" then
                    nop_cnt <= (others => '0');
                    nop_en  <= '0';
                  else
                  end if;

                else
                  row_sel <= row_sel;
                end if;
              else
                bank_sel <= bank_sel;
              end if;
            else
              column_sel <= column_sel;
            end if;
          end if;

        end if;

      elsif R_W = '0' and EN = '0' then
        addr_en_ram <= '0';
        nop_en      <= '0';
        nop_cnt     <= (others => '0');
        
      else

        addr_en_ram <= '0';
        burst_cnt   <= burst_cnt;

      end if;
    end if;
  end process addr_gen;

  clk_tb <= SYSCLK;                     --clk200_buf1;


--  clk200_buffer1 : BUFG
--    port map (
--      O => clk200_buf1,                 -- Clock buffer output
--      I => SYSCLK                       -- Clock buffer input
--      );


  ram_contr : ddr2_mem
    port map
    (
      cntrl0_DDR2_DQ            => cntrl0_DDR2_DQ,
      cntrl0_DDR2_A             => cntrl0_DDR2_A,
      cntrl0_DDR2_BA            => cntrl0_DDR2_BA,
      cntrl0_DDR2_RAS_N         => cntrl0_DDR2_RAS_N,
      cntrl0_DDR2_CAS_N         => cntrl0_DDR2_CAS_N,
      cntrl0_DDR2_WE_N          => cntrl0_DDR2_WE_N,
      cntrl0_DDR2_RESET_N       => cntrl0_DDR2_RESET_N,
      cntrl0_DDR2_CS_N          => cntrl0_DDR2_CS_N,
      cntrl0_DDR2_ODT           => cntrl0_DDR2_ODT,
      cntrl0_DDR2_CKE           => cntrl0_DDR2_CKE,
      cntrl0_DDR2_DM            => cntrl0_DDR2_DM,
      SYS_CLK_P                 => clk_tb,
      SYS_CLK_N                 => '0',
      CLK200_P                  => '0',
      CLK200_N                  => '0',
      SYS_RESET_IN              => res_in,
      cntrl0_CLK_TB             => open,
      cntrl0_RESET_TB           => res_out,
      cntrl0_WDF_ALMOST_FULL    => data_full,
      cntrl0_AF_ALMOST_FULL     => addr_full,
      cntrl0_READ_DATA_VALID    => valid,
      cntrl0_APP_WDF_WREN       => data_en,
      cntrl0_APP_AF_WREN        => addr_en,
      cntrl0_BURST_LENGTH       => open,
      cntrl0_APP_AF_ADDR        => addr_ram,
      cntrl0_READ_DATA_FIFO_OUT => read_data1,
      cntrl0_APP_WDF_DATA       => write_data,
      cntrl0_APP_MASK_DATA      => mask,
      cntrl0_DDR2_DQS           => cntrl0_DDR2_DQS,
      cntrl0_DDR2_DQS_N         => cntrl0_DDR2_DQS_N,
      cntrl0_DDR2_CK            => cntrl0_DDR2_CK,
      cntrl0_DDR2_CK_N          => cntrl0_DDR2_CK_N,
      LOCK_IN                   => res_in
      );

  DATA_OUT <= read_data1 when rising_edge(clk_tb);

end ddr2_usr_be_arc;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:04 2008 for BCM-AAA by  1.5.7.1-20081012