BCM-AAA: main_components.vhd Source File

00001 --**************************************************************
00002 --*                                                            *
00003 --*     The source code for the ATLAS BCM "AAA" FPGA is made   *
00004 --*     available via the GNU General Public License (GPL)     *
00005 --*     unless otherwise stated below.                         *
00006 --*                                                            *
00007 --*     In case of problems/questions/bug reports etc. please  *
00008 --*     contact michael.niegl@cern.ch                          *
00009 --*                                                            *
00010 --**************************************************************
00011 
00012 --**************************************************************
00013 --*                                                            *
00014 --*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/main/main_components.vhd,v $
00015 --*  $Revision: 2.45.2.13 $                                         *
00016 --*  $Name: dev $                                                 *
00017 --*  $Author: mniegl $                                         *
00018 --*  $Date: 2008/11/03 19:09:26 $                              *
00019 
00020 
00021 --*                                                            *
00022 --**************************************************************
00023 
00024 
00025 
00026 library ieee;
00027 
00028 use ieee.std_logic_1164.all;
00029 
00030 
00031 package main_components is
00032 
00033 --*******************************************************************************
00034 --*                                   constants
00035 --*******************************************************************************
00036   constant gnd          : std_logic                     := '0';
00037   constant gnd_vec      : std_logic_vector(7 downto 0)  := (others => gnd);
00038   constant gnd_vec_long : std_logic_vector(99 downto 0) := (others => gnd);
00039 
00040 --*******************************************************************************
00041 --*                                   type defs
00042 --*******************************************************************************
00043   type global_states is (g_waitriostartup, g_calib, g_idle, g_capture,
00044                          g_reset, g_read, g_error, g_freeze, g_armed);
00045   type lcd_line is array (0 to 15) of std_logic_vector(7 downto 0);
00046   type lcd_states is (lcdinit, lcdwrite);
00047   type read_out_states is (r_idle, r_proc, r_raw, r_int, r_err);
00048   type emac_states is (e_idle, e_dump, e_stat, e_ack, e_fillstat, e_tdaq, e_filltdaq);
00049   type err_states is (err_no, err_yes);
00050 
00051 --*******************************************************************************
00052 --*                             component declarations
00053 --*******************************************************************************
00054 
00055   component clocks
00056     port(
00057       RESET                    : in  std_logic;
00058       SYSCLK                   : in  std_logic;
00059       REFCLK                   : in  std_logic;
00060       BCLK4X                   : in  std_logic;
00061       UPPER_MGTCLK_PAD_P_IN_EX : in  std_logic_vector(1 downto 0);
00062       UPPER_MGTCLK_PAD_N_IN_EX : in  std_logic_vector(1 downto 0);
00063       SYSCLK_INT               : out std_logic;
00064       REFCLK_P                 : out std_logic;
00065       REFCLK_N                 : out std_logic;
00066       DDRCLK                   : out std_logic;
00067       BCLK                     : out std_logic;
00068       BCLK2X_P                 : out std_logic;
00069       BCLK2X_N                 : out std_logic;
00070       BCLK4X_P                 : out std_logic;
00071       BCLK4X_N                 : out std_logic;
00072       RIOCLK_1                 : out std_logic;
00073       RIOCLK_2                 : out std_logic;
00074       EMAC_CLK                 : out std_logic;
00075       SATA_CLK                 : out std_logic;
00076       SATA_LOGIC_CLK           : out std_logic;
00077       CLK_50MHz_OUT            : out std_logic;
00078       INTTRIG_CLK              : out std_logic;
00079       CLK_HZ                   : out std_logic;
00080       XTAL_SEL                 : out std_logic;
00081       CLK_DET                  : in  std_logic;
00082       LOCK                     : out std_logic
00083       );
00084   end component;
00085 
00086 
00087   component rio2mem
00088     port(
00089       BCLK                : in    std_logic;
00090       RIOCLK_1            : in    std_logic;
00091       RIOCLK_2            : in    std_logic;
00092       BCLK2X_P            : in    std_logic;
00093       BCLK2X_N            : in    std_logic;
00094       BCLK4X_P            : in    std_logic;
00095       BCLK4X_N            : in    std_logic;
00096       REFCLK_P            : in    std_logic;
00097       REFCLK_N            : in    std_logic;
00098       DDRCLK              : in    std_logic;
00099       EMAC_CLK            : in    std_logic;
00100       SATA_REF_CLK        : in    std_logic;
00101       SATA_LOGIC_CLK      : in    std_logic;
00102       CLK_50              : in    std_logic;
00103       CLK_HZ              : in    std_logic;
00104       XT_CLK_DET          : in    std_logic;
00105       GP_ERR_FLAG         : out   std_logic;
00106       MODE                : out   std_logic;
00107       RESET               : in    std_logic;
00108       CALIBRATE_RIOS      : in    std_logic;
00109       SATA_OK             : out   std_logic;
00110       RES_PC              : out   std_logic;
00111       TRIG_PC             : out   std_logic;
00112       STOP_PC             : out   std_logic;
00113       FORCE_PM            : out   std_logic;
00114       READ_READY          : in    std_logic;
00115       READ_OVER           : in    std_logic;
00116       RXP_SATA_IN         : in    std_logic_vector (1 downto 0);
00117       RXN_SATA_IN         : in    std_logic_vector (1 downto 0);
00118       TXP_SATA_OUT        : out   std_logic_vector (1 downto 0);
00119       TXN_SATA_OUT        : out   std_logic_vector (1 downto 0);
00120       RXN_C_IE            : in    std_logic_vector(1 downto 0);
00121       RXP_C_IE            : in    std_logic_vector(1 downto 0);
00122       RXN_C_AH            : in    std_logic_vector(1 downto 0);
00123       RXP_C_AH            : in    std_logic_vector(1 downto 0);
00124       RXN_A_WM            : in    std_logic_vector(1 downto 0);
00125       RXP_A_WM            : in    std_logic_vector(1 downto 0);
00126       RXN_A_HH            : in    std_logic_vector(1 downto 0);
00127       RXP_A_HH            : in    std_logic_vector(1 downto 0);
00128       CAPTURE             : in    std_logic;
00129       cntrl0_DDR_DQ       : inout std_logic_vector(31 downto 0);
00130       cntrl0_DDR_DQS      : inout std_logic_vector(3 downto 0);
00131       cntrl0_DDR2_DQ      : inout std_logic_vector(63 downto 0);
00132       cntrl0_DDR2_DQS     : inout std_logic_vector(7 downto 0);
00133       cntrl0_DDR2_DQS_N   : inout std_logic_vector(7 downto 0);
00134       CHECK               : out   std_logic;
00135       RIOS_READY          : out   std_logic;
00136       CAL_DONE            : out   std_logic;
00137       SEND_ARP_ANN        : in    std_logic;
00138       LOCK_OUT            : out   std_logic;
00139       MAC_LOCK            : out   std_logic;
00140       READ_OUT            : in    std_logic;
00141       READ_DONE           : out   std_logic;
00142       TRIGGER_INHIBIT_N   : out   std_logic;
00143       MAIN_FSM_ST         : in    std_logic_vector(7 downto 0);
00144       TXN_C_IE            : out   std_logic_vector(1 downto 0);
00145       TXP_C_IE            : out   std_logic_vector(1 downto 0);
00146       TXN_C_AH            : out   std_logic_vector(1 downto 0);
00147       TXP_C_AH            : out   std_logic_vector(1 downto 0);
00148       TXN_A_WM            : out   std_logic_vector(1 downto 0);
00149       TXP_A_WM            : out   std_logic_vector(1 downto 0);
00150       TXN_A_HH            : out   std_logic_vector(1 downto 0);
00151       TXP_A_HH            : out   std_logic_vector(1 downto 0);
00152       MASK_IRENA          : out   std_logic;
00153       MASK_EWA            : out   std_logic;
00154       MASK_ANDREJ         : out   std_logic;
00155       MASK_HEINZ          : out   std_logic;
00156       MASK_MARKO          : out   std_logic;
00157       MASK_WILLIAM        : out   std_logic;
00158       MASK_HARRIS         : out   std_logic;
00159       MASK_HELMUT         : out   std_logic;
00160       OR_CH1              : out   std_logic;
00161       OR_CH2              : out   std_logic;
00162       cntrl0_DDR_A        : out   std_logic_vector(12 downto 0);
00163       cntrl0_DDR_BA       : out   std_logic_vector(1 downto 0);
00164       cntrl0_DDR_CKE      : out   std_logic;
00165       cntrl0_DDR_CS_N     : out   std_logic;
00166       cntrl0_DDR_RAS_N    : out   std_logic;
00167       cntrl0_DDR_CAS_N    : out   std_logic;
00168       cntrl0_DDR_WE_N     : out   std_logic;
00169       cntrl0_DDR_DM       : out   std_logic_vector(3 downto 0);
00170       cntrl0_DDR_CK       : out   std_logic;
00171       cntrl0_DDR_CK_N     : out   std_logic;
00172       cntrl0_DDR2_A       : out   std_logic_vector(13 downto 0);
00173       cntrl0_DDR2_BA      : out   std_logic_vector(1 downto 0);
00174       cntrl0_DDR2_RAS_N   : out   std_logic;
00175       cntrl0_DDR2_CAS_N   : out   std_logic;
00176       cntrl0_DDR2_WE_N    : out   std_logic;
00177       cntrl0_DDR2_RESET_N : out   std_logic;
00178       cntrl0_DDR2_CS_N    : out   std_logic;
00179       cntrl0_DDR2_ODT     : out   std_logic;
00180       cntrl0_DDR2_CKE     : out   std_logic;
00181       cntrl0_DDR2_DM      : out   std_logic_vector(7 downto 0);
00182       cntrl0_DDR2_CK      : out   std_logic;
00183       cntrl0_DDR2_CK_N    : out   std_logic;
00184       gmii_rx_clk         : in    std_logic;
00185       gmii_rx_dv          : in    std_logic;
00186       gmii_rx_er          : in    std_logic;
00187       gmii_rxd            : in    std_logic_vector(0 to 7);
00188       mii_tx_clk          : in    std_logic;
00189       mdio                : inout std_logic;
00190       gmii_tx_en          : out   std_logic;
00191       gmii_tx_er          : out   std_logic;
00192       gmii_txd            : out   std_logic_vector(0 to 3);
00193       MDC_0               : out   std_logic;
00194       phy_rst_n           : out   std_logic;
00195       TRIG_EXT            : in    std_logic;
00196       SL_LFF              : in    std_logic;
00197       SL_LDOWN            : in    std_logic;
00198       SL_LRL              : in    std_logic_vector(3 downto 0);  --* not used!
00199       SL_UCLK             : out   std_logic;
00200       SL_UD               : out   std_logic_vector(31 downto 0);
00201       SL_URESET           : out   std_logic;
00202       SL_UTEST            : out   std_logic;
00203       SL_UWEN             : out   std_logic;
00204       SL_UCTRL            : out   std_logic;
00205       SL_UDW              : out   std_logic_vector(1 downto 0);
00206       BUSY                : out   std_logic;
00207       ORBIT               : in    std_logic;
00208       L1A                 : in    std_logic;
00209       ECR                 : in    std_logic;
00210       BCR                 : in    std_logic;
00211       TRIGGER_TYPE        : in    std_logic_vector(8 downto 1);
00212       CTP                 : out   std_logic_vector(9 downto 1);
00213       INJECT_PERM_1       : out   std_logic;
00214       INJECT_PERM_2       : out   std_logic;
00215       BEAM_PERM_1         : out   std_logic;
00216       BEAM_PERM_2         : out   std_logic;
00217       DSS_WARNING_1       : out   std_logic;
00218       DSS_WARNING_2       : out   std_logic;
00219       DSS_ABORT_1         : out   std_logic;
00220       DSS_ABORT_2         : out   std_logic;
00221       GOTO_RD             : out   std_logic;
00222       L1A_DISP            : in    std_logic;
00223       RIOERR              : out   std_logic;
00224       RIOERR_TYPE         : out   std_logic_vector(7 downto 0);
00225       SEND_ERR_MSG        : in    std_logic;
00226       ERROR_CODE          : in    std_logic_vector(7 downto 0)
00227       );
00228   end component;
00229 
00230 
00231   component delay
00232     generic (i : integer range 0 to 99 := 00);
00233     port(
00234       A     : in  std_logic;
00235       CLK   : in  std_logic;
00236       RES   : in  std_logic;
00237       A_DEL : out std_logic
00238       );
00239   end component;
00240 
00241 
00242   component edge
00243     port(
00244       CLK   : in  std_logic;
00245       A     : in  std_logic;
00246       PULSE : out std_logic
00247       );
00248   end component;
00249 
00250 
00251   component edge_fal
00252     port(
00253       CLK   : in  std_logic;
00254       A     : in  std_logic;
00255       PULSE : out std_logic
00256       );
00257   end component;
00258 
00259 
00260   component busy
00261     generic (DEAD : integer range 0 to 30 := 10);
00262     port(
00263       CLK      : in  std_logic;
00264       RES      : in  std_logic;
00265       EN       : in  std_logic;
00266       TRIG_IN  : in  std_logic;
00267       TRIG_OUT : out std_logic
00268       );
00269   end component;
00270 
00271 
00272   component rios_all
00273     port(
00274       BCLK                 : in  std_logic;
00275       BCLK4X               : in  std_logic;
00276       BCLK2X               : in  std_logic;
00277       RIOCLK_1             : in  std_logic;
00278       RIOCLK_2             : in  std_logic;
00279       EN                   : in  std_logic;
00280       RESET                : in  std_logic;
00281       SEP_RESET            : in  std_logic_vector(7 downto 0);
00282       CALIBRATE_RIOS       : in  std_logic;
00283       COARSE_TIME_IRENA    : in  std_logic_vector(7 downto 0);
00284       COARSE_TIME_EWA      : in  std_logic_vector(7 downto 0);
00285       COARSE_TIME_ANDREJ   : in  std_logic_vector(7 downto 0);
00286       COARSE_TIME_HEINZ    : in  std_logic_vector(7 downto 0);
00287       COARSE_TIME_MARKO    : in  std_logic_vector(7 downto 0);
00288       COARSE_TIME_WILLIAM  : in  std_logic_vector(7 downto 0);
00289       COARSE_TIME_HARRIS   : in  std_logic_vector(7 downto 0);
00290       COARSE_TIME_HELMUT   : in  std_logic_vector(7 downto 0);
00291       ADJUST_TIME_IRENA    : in  integer range 0 to 32 := 0;
00292       ADJUST_TIME_EWA      : in  integer range 0 to 32 := 0;
00293       ADJUST_TIME_ANDREJ   : in  integer range 0 to 32 := 0;
00294       ADJUST_TIME_HEINZ    : in  integer range 0 to 32 := 0;
00295       ADJUST_TIME_MARKO    : in  integer range 0 to 32 := 0;
00296       ADJUST_TIME_WILLIAM  : in  integer range 0 to 32 := 0;
00297       ADJUST_TIME_HARRIS   : in  integer range 0 to 32 := 0;
00298       ADJUST_TIME_HELMUT   : in  integer range 0 to 32 := 0;
00299       ADJUST_TIME_IRENA2   : in  integer range 0 to 32 := 0;
00300       ADJUST_TIME_EWA2     : in  integer range 0 to 32 := 0;
00301       ADJUST_TIME_ANDREJ2  : in  integer range 0 to 32 := 0;
00302       ADJUST_TIME_HEINZ2   : in  integer range 0 to 32 := 0;
00303       ADJUST_TIME_MARKO2   : in  integer range 0 to 32 := 0;
00304       ADJUST_TIME_WILLIAM2 : in  integer range 0 to 32 := 0;
00305       ADJUST_TIME_HARRIS2  : in  integer range 0 to 32 := 0;
00306       ADJUST_TIME_HELMUT2  : in  integer range 0 to 32 := 0;
00307       RXN_C_IE             : in  std_logic_vector(1 downto 0);
00308       RXP_C_IE             : in  std_logic_vector(1 downto 0);
00309       RXN_C_AH             : in  std_logic_vector(1 downto 0);
00310       RXP_C_AH             : in  std_logic_vector(1 downto 0);
00311       RXN_A_WM             : in  std_logic_vector(1 downto 0);
00312       RXP_A_WM             : in  std_logic_vector(1 downto 0);
00313       RXN_A_HH             : in  std_logic_vector(1 downto 0);
00314       RXP_A_HH             : in  std_logic_vector(1 downto 0);
00315       RIOS_READY           : out std_logic;
00316       DONE                 : out std_logic;
00317       CHECK                : out std_logic;
00318       LOCK_OUT             : out std_logic;
00319       TXN_C_IE             : out std_logic_vector(1 downto 0);
00320       TXP_C_IE             : out std_logic_vector(1 downto 0);
00321       TXN_C_AH             : out std_logic_vector(1 downto 0);
00322       TXP_C_AH             : out std_logic_vector(1 downto 0);
00323       TXN_A_WM             : out std_logic_vector(1 downto 0);
00324       TXP_A_WM             : out std_logic_vector(1 downto 0);
00325       TXN_A_HH             : out std_logic_vector(1 downto 0);
00326       TXP_A_HH             : out std_logic_vector(1 downto 0);
00327       CAL_IRENA            : in  std_logic;
00328       CAL_EWA              : in  std_logic;
00329       CAL_ANDREJ           : in  std_logic;
00330       CAL_HEINZ            : in  std_logic;
00331       CAL_MARKO            : in  std_logic;
00332       CAL_WILLIAM          : in  std_logic;
00333       CAL_HARRIS           : in  std_logic;
00334       CAL_HELMUT           : in  std_logic;
00335       MASK_IRENA           : out std_logic;
00336       MASK_EWA             : out std_logic;
00337       MASK_ANDREJ          : out std_logic;
00338       MASK_HEINZ           : out std_logic;
00339       MASK_MARKO           : out std_logic;
00340       MASK_WILLIAM         : out std_logic;
00341       MASK_HARRIS          : out std_logic;
00342       MASK_HELMUT          : out std_logic;
00343       RX_LOCK1             : out std_logic;
00344       RX_LOCK2             : out std_logic;
00345       RX_LOCK3             : out std_logic;
00346       RX_LOCK4             : out std_logic;
00347       RX_LOCK5             : out std_logic;
00348       RX_LOCK6             : out std_logic;
00349       RX_LOCK7             : out std_logic;
00350       RX_LOCK8             : out std_logic;
00351       TX_LOCK1             : out std_logic;
00352       TX_LOCK2             : out std_logic;
00353       TX_LOCK3             : out std_logic;
00354       TX_LOCK4             : out std_logic;
00355       TX_LOCK5             : out std_logic;
00356       TX_LOCK6             : out std_logic;
00357       TX_LOCK7             : out std_logic;
00358       TX_LOCK8             : out std_logic;
00359       RX_READY1            : out std_logic;
00360       RX_READY2            : out std_logic;
00361       RX_READY3            : out std_logic;
00362       RX_READY4            : out std_logic;
00363       RX_READY5            : out std_logic;
00364       RX_READY6            : out std_logic;
00365       RX_READY7            : out std_logic;
00366       RX_READY8            : out std_logic;
00367       TX_READY1            : out std_logic;
00368       TX_READY2            : out std_logic;
00369       TX_READY3            : out std_logic;
00370       TX_READY4            : out std_logic;
00371       TX_READY5            : out std_logic;
00372       TX_READY6            : out std_logic;
00373       TX_READY7            : out std_logic;
00374       TX_READY8            : out std_logic;
00375       MULT_IRENA           : out std_logic_vector(7 downto 0);
00376       MULT_EWA             : out std_logic_vector(7 downto 0);
00377       MULT_ANDREJ          : out std_logic_vector(7 downto 0);
00378       MULT_HEINZ           : out std_logic_vector(7 downto 0);
00379       MULT_MARKO           : out std_logic_vector(7 downto 0);
00380       MULT_WILLIAM         : out std_logic_vector(7 downto 0);
00381       MULT_HARRIS          : out std_logic_vector(7 downto 0);
00382       MULT_HELMUT          : out std_logic_vector(7 downto 0);
00383       PROC_DATA            : out std_logic_vector(191 downto 0);
00384       RAW_DATA             : out std_logic_vector(255 downto 0)
00385       );
00386   end component;
00387 
00388 
00389   component ddr_data_buffer
00390     port(
00391       CLK_A    : in  std_logic;
00392       CLK_B    : in  std_logic;
00393       RESET    : in  std_logic;
00394       WEN      : in  std_logic;
00395       REN      : in  std_logic;
00396       DATA_IN  : in  std_logic_vector(191 downto 0);
00397       EMPTY    : out std_logic;
00398       DATA_OUT : out std_logic_vector(63 downto 0)
00399       );
00400   end component;
00401 
00402 
00403   component ram_user_backend
00404     port(
00405       SYSCLK_P         : in    std_logic;
00406       SYSCLK_N         : in    std_logic;
00407       CLK200_P         : in    std_logic;
00408       CLK200_N         : in    std_logic;
00409       SYS_RESET_IN     : in    std_logic;
00410       ADDR_RES         : in    std_logic;
00411       ADDR_OVR         : out   std_logic;
00412       R_W              : in    std_logic;
00413       EN               : in    std_logic;
00414       cntrl0_DDR_DQ    : inout std_logic_vector(31 downto 0);
00415       cntrl0_DDR_DQS   : inout std_logic_vector(3 downto 0);
00416       cntrl0_DDR_A     : out   std_logic_vector(12 downto 0);
00417       cntrl0_DDR_BA    : out   std_logic_vector(1 downto 0);
00418       cntrl0_DDR_CKE   : out   std_logic;
00419       cntrl0_DDR_CS_N  : out   std_logic;
00420       cntrl0_DDR_RAS_N : out   std_logic;
00421       cntrl0_DDR_CAS_N : out   std_logic;
00422       cntrl0_DDR_WE_N  : out   std_logic;
00423       cntrl0_DDR_DM    : out   std_logic_vector(3 downto 0);
00424       cntrl0_DDR_CK    : out   std_logic;
00425       cntrl0_DDR_CK_N  : out   std_logic;
00426       LED_CONTR        : out   std_logic;
00427       LED_R            : out   std_logic;
00428       HALT             : out   std_logic;
00429       RDBURST_END      : out   std_logic;
00430       VALID_OUT        : out   std_logic;
00431       DATA_IN          : in    std_logic_vector(63 downto 0);
00432       READ_DATA_OUT    : out   std_logic_vector(63 downto 0)
00433       );
00434   end component;
00435 
00436 
00437   component ddr2_data_buffer
00438     port(
00439       CLKA     : in  std_logic;
00440       CLKB     : in  std_logic;
00441       RESET    : in  std_logic;
00442       WEN      : in  std_logic;
00443       REN      : in  std_logic;
00444       DATA_IN  : in  std_logic_vector(255 downto 0);
00445       EMPTY    : out std_logic;
00446       DATA_OUT : out std_logic_vector(127 downto 0)
00447       );
00448   end component;
00449 
00450 
00451   component ddr2_usr_be
00452     port(
00453       SYSCLK              : in    std_logic;
00454       CLK_SLOW            : in    std_logic;
00455       RESET_IN            : in    std_logic;
00456       ADDR_RES            : in    std_logic;
00457       cntrl0_DDR2_DQ      : inout std_logic_vector(63 downto 0);
00458       cntrl0_DDR2_DQS     : inout std_logic_vector(7 downto 0);
00459       cntrl0_DDR2_DQS_N   : inout std_logic_vector(7 downto 0);
00460       cntrl0_DDR2_A       : out   std_logic_vector(13 downto 0);
00461       cntrl0_DDR2_BA      : out   std_logic_vector(1 downto 0);
00462       cntrl0_DDR2_RAS_N   : out   std_logic;
00463       cntrl0_DDR2_CAS_N   : out   std_logic;
00464       cntrl0_DDR2_WE_N    : out   std_logic;
00465       cntrl0_DDR2_RESET_N : out   std_logic;
00466       cntrl0_DDR2_CS_N    : out   std_logic;
00467       cntrl0_DDR2_ODT     : out   std_logic;
00468       cntrl0_DDR2_CKE     : out   std_logic;
00469       cntrl0_DDR2_DM      : out   std_logic_vector(7 downto 0);
00470       cntrl0_DDR2_CK      : out   std_logic;
00471       cntrl0_DDR2_CK_N    : out   std_logic;
00472       COMP_OUT1           : out   std_logic;
00473       COMP_OUT2           : out   std_logic;
00474       LED_CONTR           : out   std_logic;
00475       LED_R               : out   std_logic;
00476       VALID_OUT           : out   std_logic;
00477       R_W                 : in    std_logic;
00478       FETCH               : out   std_logic;
00479       EN                  : in    std_logic;
00480       RDBURST_END         : out   std_logic;
00481       ADDR_OVR            : out   std_logic;
00482       DATA_IN             : in    std_logic_vector(127 downto 0);
00483       DATA_OUT            : out   std_logic_vector(127 downto 0)
00484       );
00485   end component;
00486 
00487 
00488   component eth_buf
00489     port(
00490       CLK_WR   : in  std_logic;
00491       CLK_RD   : in  std_logic;
00492       RES      : in  std_logic;
00493       RD       : in  std_logic;
00494       WR       : in  std_logic;
00495       DATA_IN  : in  std_logic_vector(127 downto 0);
00496       DATA_OUT : out std_logic_vector(7 downto 0)
00497       );
00498   end component;
00499 
00500 
00501   component ethernet_top
00502     port
00503       (
00504         RESET           : in    std_logic;
00505         PKT_CNT_RST     : in    std_logic;
00506         START           : in    std_logic;
00507         INC_PKTCNT      : in    std_logic;
00508         CYCLE           : in    std_logic;
00509         SEND_PKT_SE     : in    std_logic;
00510         STATUS_PKT      : in    std_logic;
00511         TDAQ_STATUS_PKT : in    std_logic;
00512         ARP_ANN         : in    std_logic;
00513         RD_READY        : in    std_logic;
00514         RD_OVER         : in    std_logic;
00515         DATATYPE        : in    std_logic;
00516         ETH_EN          : in    std_logic;
00517         BYTE_IN         : in    std_logic_vector(7 downto 0);
00518         GET_BYTE        : out   std_logic;
00519         PKT_DONE        : out   std_logic;
00520         CHK_DONE        : out   std_logic;
00521         GET_UDPCHK      : out   std_logic;
00522         UDPCHK_IN_1     : in    std_logic_vector(15 downto 0);
00523         UDPCHK_IN_2     : in    std_logic_vector(15 downto 0);
00524         SYSCLK          : in    std_logic;
00525         gmii_rx_clk     : in    std_logic;
00526         gmii_rx_dv      : in    std_logic;
00527         gmii_rx_er      : in    std_logic;
00528         gmii_rxd        : in    std_logic_vector(0 to 7);
00529         mii_tx_clk      : in    std_logic;
00530         mdio            : inout std_logic;
00531         gmii_tx_en      : out   std_logic;
00532         gmii_tx_er      : out   std_logic;
00533         gmii_txd        : out   std_logic_vector(0 to 3);
00534         MDC_0           : out   std_logic;
00535         phy_rst_n       : out   std_logic;
00536         RXDATA          : out   std_logic_vector(7 downto 0);
00537         RXVLD           : out   std_logic;
00538         PACKET_NR       : out   std_logic_vector(19 downto 0);
00539         DATA_TYPE       : out   std_logic_vector(11 downto 0);
00540         LOCK            : out   std_logic;
00541         CONTR_LED       : out   std_logic
00542         );
00543   end component;
00544 
00545 
00546   component cnt_ddr2_rd
00547     port(
00548       RESET : in  std_logic;
00549       CLK   : in  std_logic;
00550       EN    : in  std_logic;
00551       DONE  : out std_logic
00552       );
00553   end component;
00554 
00555 
00556   component cnt_ddr_rd
00557     port(
00558       RESET : in  std_logic;
00559       CLK   : in  std_logic;
00560       EN    : in  std_logic;
00561       DONE  : out std_logic
00562       );
00563   end component;
00564 
00565 
00566   component lvl1_buf
00567     port(
00568       RESET      : in  std_logic;
00569       CLKWR      : in  std_logic;
00570       CLKRD      : in  std_logic;
00571       WR_BID     : in  std_logic_vector (11 downto 0) := "000000000000";
00572       RD_BID     : in  std_logic_vector (11 downto 0) := "000000000000";
00573       DATA_IN    : in  std_logic_vector (175 downto 0);
00574       EN_B       : in  std_logic;
00575       WE         : in  std_logic;
00576       VLD        : out std_logic;
00577       NUM        : in  std_logic_vector(6 downto 0)   := "0000001";
00578       all_READ   : out std_logic;
00579       PAUSE      : in  std_logic;
00580       FINISH     : in  std_logic;
00581       READ_ERROR : out std_logic;
00582       DATA_OUT   : out std_logic_vector(191 downto 0) := (others => '0')
00583       );
00584   end component;
00585 
00586 
00587   component l1a_fifo
00588     port (
00589       clk   : in  std_logic;
00590       din   : in  std_logic_vector(43 downto 0);
00591       rd_en : in  std_logic;
00592       srst  : in  std_logic;
00593       wr_en : in  std_logic;
00594       dout  : out std_logic_vector(43 downto 0);
00595       empty : out std_logic;
00596       full  : out std_logic
00597       );
00598   end component;
00599 
00600 
00601 
00602   component rio_or
00603     port(
00604       CH1    : in  std_logic_vector(31 downto 0);
00605       CH2    : in  std_logic_vector(31 downto 0);
00606       CLK    : in  std_logic;
00607       OR_CH1 : out std_logic;
00608       OR_CH2 : out std_logic
00609       );
00610   end component;
00611 
00612 
00613   component delta_t_ac_top
00614     port(
00615       CLK           : in  std_logic;
00616       UPPER_BOUND_A : in  std_logic_vector(5 downto 0) := "101110";
00617       LOWER_BOUND_A : in  std_logic_vector(5 downto 0) := "010000";
00618       UPPER_BOUND_C : in  std_logic_vector(5 downto 0) := "101110";
00619       LOWER_BOUND_C : in  std_logic_vector(5 downto 0) := "010000";
00620       IRENA1        : in  std_logic_vector(7 downto 0);
00621       EWA1          : in  std_logic_vector(7 downto 0);
00622       HEINZ1        : in  std_logic_vector(7 downto 0);
00623       ANDREJ1       : in  std_logic_vector(7 downto 0);
00624       MARKO1        : in  std_logic_vector(7 downto 0);
00625       WILLIAM1      : in  std_logic_vector(7 downto 0);
00626       HARRIS1       : in  std_logic_vector(7 downto 0);
00627       HELMUT1       : in  std_logic_vector(7 downto 0);
00628       S_IRENA1      : in  std_logic;
00629       S_EWA1        : in  std_logic;
00630       S_HEINZ1      : in  std_logic;
00631       S_ANDREJ1     : in  std_logic;
00632       S_MARKO1      : in  std_logic;
00633       S_WILLIAM1    : in  std_logic;
00634       S_HARRIS1     : in  std_logic;
00635       S_HELMUT1     : in  std_logic;
00636       IRENA2        : in  std_logic_vector(7 downto 0);
00637       EWA2          : in  std_logic_vector(7 downto 0);
00638       HEINZ2        : in  std_logic_vector(7 downto 0);
00639       ANDREJ2       : in  std_logic_vector(7 downto 0);
00640       MARKO2        : in  std_logic_vector(7 downto 0);
00641       WILLIAM2      : in  std_logic_vector(7 downto 0);
00642       HARRIS2       : in  std_logic_vector(7 downto 0);
00643       HELMUT2       : in  std_logic_vector(7 downto 0);
00644       S_IRENA2      : in  std_logic;
00645       S_EWA2        : in  std_logic;
00646       S_HEINZ2      : in  std_logic;
00647       S_ANDREJ2     : in  std_logic;
00648       S_MARKO2      : in  std_logic;
00649       S_WILLIAM2    : in  std_logic;
00650       S_HARRIS2     : in  std_logic;
00651       S_HELMUT2     : in  std_logic;
00652       VLD           : out std_logic;
00653       HITCH_11      : out std_logic_vector(2 downto 0);
00654       HITCH_12      : out std_logic_vector(2 downto 0);
00655       HITCH_21      : out std_logic_vector(2 downto 0);
00656       HITCH_22      : out std_logic_vector(2 downto 0);
00657       DELTA_TOUT    : out std_logic_vector(6 downto 0)
00658       );
00659   end component;
00660 
00661 
00662   component intime
00663     port (
00664       CLK           : in  std_logic;
00665       UPPER_BOUND_A : in  std_logic_vector(5 downto 0) := "101110";
00666       LOWER_BOUND_A : in  std_logic_vector(5 downto 0) := "010000";
00667       UPPER_BOUND_C : in  std_logic_vector(5 downto 0) := "101110";
00668       LOWER_BOUND_C : in  std_logic_vector(5 downto 0) := "010000";
00669       IRENA1        : in  std_logic_vector (7 downto 0);
00670       EWA1          : in  std_logic_vector (7 downto 0);
00671       HEINZ1        : in  std_logic_vector (7 downto 0);
00672       ANDREJ1       : in  std_logic_vector (7 downto 0);
00673       MARKO1        : in  std_logic_vector (7 downto 0);
00674       WILLIAM1      : in  std_logic_vector (7 downto 0);
00675       HARRIS1       : in  std_logic_vector (7 downto 0);
00676       HELMUT1       : in  std_logic_vector (7 downto 0);
00677       IRENA2        : in  std_logic_vector (7 downto 0);
00678       EWA2          : in  std_logic_vector (7 downto 0);
00679       HEINZ2        : in  std_logic_vector (7 downto 0);
00680       ANDREJ2       : in  std_logic_vector (7 downto 0);
00681       MARKO2        : in  std_logic_vector (7 downto 0);
00682       WILLIAM2      : in  std_logic_vector (7 downto 0);
00683       HARRIS2       : in  std_logic_vector (7 downto 0);
00684       HELMUT2       : in  std_logic_vector (7 downto 0);
00685       S_IRENA1      : in  std_logic;
00686       S_EWA1        : in  std_logic;
00687       S_HEINZ1      : in  std_logic;
00688       S_ANDREJ1     : in  std_logic;
00689       S_MARKO1      : in  std_logic;
00690       S_WILLIAM1    : in  std_logic;
00691       S_HARRIS1     : in  std_logic;
00692       S_HELMUT1     : in  std_logic;
00693       S_IRENA2      : in  std_logic;
00694       S_EWA2        : in  std_logic;
00695       S_HEINZ2      : in  std_logic;
00696       S_ANDREJ2     : in  std_logic;
00697       S_MARKO2      : in  std_logic;
00698       S_WILLIAM2    : in  std_logic;
00699       S_HARRIS2     : in  std_logic;
00700       S_HELMUT2     : in  std_logic;
00701       IRENA1_O      : out std_logic_vector (7 downto 0);
00702       EWA1_O        : out std_logic_vector (7 downto 0);
00703       HEINZ1_O      : out std_logic_vector (7 downto 0);
00704       ANDREJ1_O     : out std_logic_vector (7 downto 0);
00705       MARKO1_O      : out std_logic_vector (7 downto 0);
00706       WILLIAM1_O    : out std_logic_vector (7 downto 0);
00707       HARRIS1_O     : out std_logic_vector (7 downto 0);
00708       HELMUT1_O     : out std_logic_vector (7 downto 0);
00709       IRENA2_O      : out std_logic_vector (7 downto 0);
00710       EWA2_O        : out std_logic_vector (7 downto 0);
00711       HEINZ2_O      : out std_logic_vector (7 downto 0);
00712       ANDREJ2_O     : out std_logic_vector (7 downto 0);
00713       MARKO2_O      : out std_logic_vector (7 downto 0);
00714       WILLIAM2_O    : out std_logic_vector (7 downto 0);
00715       HARRIS2_O     : out std_logic_vector (7 downto 0);
00716       HELMUT2_O     : out std_logic_vector (7 downto 0);
00717       S_IRENA1_O    : out std_logic;
00718       S_EWA1_O      : out std_logic;
00719       S_HEINZ1_O    : out std_logic;
00720       S_ANDREJ1_O   : out std_logic;
00721       S_MARKO1_O    : out std_logic;
00722       S_WILLIAM1_O  : out std_logic;
00723       S_HARRIS1_O   : out std_logic;
00724       S_HELMUT1_O   : out std_logic;
00725       S_IRENA2_O    : out std_logic;
00726       S_EWA2_O      : out std_logic;
00727       S_HEINZ2_O    : out std_logic;
00728       S_ANDREJ2_O   : out std_logic;
00729       S_MARKO2_O    : out std_logic;
00730       S_WILLIAM2_O  : out std_logic;
00731       S_HARRIS2_O   : out std_logic;
00732       S_HELMUT2_O   : out std_logic);
00733   end component;
00734 
00735 
00736   component extend_test
00737     generic(LEN : integer range 0 to 63 := 0);
00738     port(
00739       CLK  : in  std_logic;
00740       RES  : in  std_logic;
00741       ENDM : out std_logic;
00742       A    : in  std_logic;
00743       Y    : out std_logic
00744       );
00745   end component;
00746 
00747 
00748   component ddr_eth_buf
00749     port(
00750       CLK_WR   : in  std_logic;
00751       CLK_RD   : in  std_logic;
00752       RES      : in  std_logic;
00753       RD       : in  std_logic;
00754       WR       : in  std_logic;
00755       DATA_IN  : in  std_logic_vector(63 downto 0);
00756       DATA_OUT : out std_logic_vector(7 downto 0)
00757       );
00758   end component;
00759 
00760 
00761   component icon
00762     port
00763       (
00764         control0 : out std_logic_vector(35 downto 0);
00765         control1 : out std_logic_vector(35 downto 0);
00766         control2 : out std_logic_vector(35 downto 0)
00767         );
00768   end component;
00769 
00770 
00771   component ila
00772     port
00773       (
00774         control : in std_logic_vector(35 downto 0);
00775         clk     : in std_logic;
00776         trig0   : in std_logic_vector(49 downto 0)
00777         );
00778   end component;
00779 
00780 
00781   component lcd_controller
00782     port (
00783       CLOCK_LCD       : in    std_logic;
00784       CLOCK_ANI_I     : in    std_logic;
00785       CLOCK_ANI_II    : in    std_logic;
00786       LINE_I          : in    lcd_line;
00787       LINE_II         : in    lcd_line;
00788       LINE_I_PAINT    : in    std_logic;
00789       LINE_II_PAINT   : in    std_logic;
00790       LINE_I_MODE     : in    std_logic_vector (1 downto 0);
00791       LINE_II_MODE    : in    std_logic_vector (1 downto 0);
00792       AUTO_REFRESH_I  : in    std_logic;
00793       AUTO_REFRESH_II : in    std_logic;
00794       BUSY            : out   std_logic;
00795       DIRECTION       : out   std_logic;
00796       RS              : out   std_logic;
00797       RW              : out   std_logic;
00798       DB              : inout std_logic_vector (7 downto 0);
00799       E               : out   std_logic
00800       );
00801   end component;
00802 
00803 
00804   component prescaler
00805     generic (divider : integer range 0 to 127 := 10);
00806     port(
00807       CLK : in  std_logic;
00808       CE  : in  std_logic;
00809       R   : in  std_logic;
00810       TC  : out std_logic
00811       );
00812   end component;
00813 
00814 
00815   component LCD
00816     port(
00817       LCDCLK        : in    std_logic;
00818       TAKE          : in    std_logic;
00819       GIVE          : in    std_logic;
00820       RES           : in    std_logic;
00821       LCD_DB        : inout std_logic_vector(7 downto 0);
00822       LCD_DIRECTION : out   std_logic;
00823       LCD_RS        : out   std_logic;
00824       LCD_RW        : out   std_logic;
00825       LCD_E         : out   std_logic
00826       );
00827   end component;
00828 
00829 
00830   component bcm_rod
00831     port(
00832       CLK                     : in  std_logic;
00833       CLK_2X                  : in  std_logic;
00834       SCLR                    : in  std_logic;
00835       rod_format_version      : in  std_logic_vector(31 downto 0) := X"03010000";
00836       rod_source_ID           : in  std_logic_vector(31 downto 0) := X"00810000";
00837       rod_run_number          : in  std_logic_vector(31 downto 0) := X"7fffffff";
00838       rod_CTP_trigger_type    : in  std_logic_vector(31 downto 0) := X"00000011";
00839       rod_detector_event_type : in  std_logic_vector(31 downto 0) := X"000000dd";
00840       data_input              : in  std_logic_vector(191 downto 0);
00841       data_lvl1id             : in  std_logic_vector(31 downto 0);
00842       data_input_valid        : in  std_logic;
00843       data_input_busy         : out std_logic;
00844       data_input_endoffrag    : in  std_logic;
00845       hola_LFF                : in  std_logic;
00846       hola_LDOWN              : in  std_logic;
00847       hola_LRL                : in  std_logic_vector(3 downto 0);
00848       hola_CLK                : out std_logic;
00849       hola_UD                 : out std_logic_vector(31 downto 0);
00850       hola_URESET             : out std_logic;
00851       hola_UTEST              : out std_logic;
00852       hola_UCTRL              : out std_logic;
00853       hola_UWEN               : out std_logic;
00854       hola_UDW                : out std_logic_vector(1 downto 0)
00855       );
00856 
00857   end component;
00858 
00859 
00860   component ltp_comm
00861     port (
00862       BCLK          : in  std_logic;
00863       RESET         : in  std_logic;
00864       ORBIT         : in  std_logic;
00865       START_RUN     : in  std_logic;
00866       L1A           : in  std_logic;
00867       BCR           : in  std_logic;
00868       ECR           : in  std_logic;
00869       ECR_LOAD_EN   : in  std_logic;
00870       ECR_LOAD      : in  std_logic_vector(7 downto 0);
00871       L1A_LOAD_EN   : in  std_logic;
00872       L1A_LOAD      : in  std_logic_vector(23 downto 0);
00873       ORBIT_LOAD_EN : in  std_logic;
00874       ORBIT_LOAD    : in  std_logic_vector(31 downto 0);
00875       EXT_EVID      : out std_logic_vector(31 downto 0);
00876       BCID          : out std_logic_vector(11 downto 0);
00877       ORBITID       : out std_logic_vector(31 downto 0)
00878       );
00879   end component;
00880 
00881 
00882   component riocheck
00883     port (
00884       CLK      : in  std_logic;
00885       RES      : in  std_logic;
00886       EN       : in  std_logic;
00887       DATA_IN  : in  std_logic_vector(255 downto 0);
00888       MASK_N   : in  std_logic_vector(7 downto 0);
00889       ERR      : out std_logic;
00890       ERR_TYPE : out std_logic_vector(7 downto 0)
00891       );
00892   end component;
00893 
00894 
00895   component side_4rios
00896     generic
00897       (
00898         PATTERN : std_logic_vector(31 downto 0) := "11110000111100001111000011110000"
00899         );
00900     port(
00901       BCLK                : in  std_logic;
00902       BCLK2X              : in  std_logic;
00903       BCLK4X              : in  std_logic;
00904       RIOCLK_1            : in  std_logic;
00905       RIOCLK_2            : in  std_logic;
00906       EN                  : in  std_logic;
00907       SET_SHIFT_1         : in  std_logic_vector(7 downto 0);
00908       SET_SHIFT_2         : in  std_logic_vector(7 downto 0);
00909       CAL                 : in  std_logic;
00910       RES                 : in  std_logic;
00911       SEP_RES             : in  std_logic_vector(3 downto 0);
00912       TX_SYSTEM_RESET_IN  : in  std_logic;
00913       RX_SYSTEM_RESET_IN  : in  std_logic;
00914       RX1N_IN_IE          : in  std_logic_vector(1 downto 0);
00915       RX1P_IN_IE          : in  std_logic_vector(1 downto 0);
00916       RX1N_IN_AH          : in  std_logic_vector(1 downto 0);
00917       RX1P_IN_AH          : in  std_logic_vector(1 downto 0);
00918       CHECK_IRENA         : out std_logic;
00919       CHECK_EWA           : out std_logic;
00920       CHECK_ANDREJ        : out std_logic;
00921       CHECK_HEINZ         : out std_logic;
00922       CAL_IRENA           : in  std_logic;
00923       CAL_EWA             : in  std_logic;
00924       CAL_ANDREJ          : in  std_logic;
00925       CAL_HEINZ           : in  std_logic;
00926       RXLOCK_OUT_IRENA    : out std_logic;
00927       TXLOCK_OUT_IRENA    : out std_logic;
00928       RXLOCK_OUT_EWA      : out std_logic;
00929       TXLOCK_OUT_EWA      : out std_logic;
00930       RXLOCK_OUT_ANDREJ   : out std_logic;
00931       TXLOCK_OUT_ANDREJ   : out std_logic;
00932       RXLOCK_OUT_HEINZ    : out std_logic;
00933       TXLOCK_OUT_HEINZ    : out std_logic;
00934       TX1N_OUT_IE         : out std_logic_vector(1 downto 0);
00935       TX1P_OUT_IE         : out std_logic_vector(1 downto 0);
00936       TX1N_OUT_AH         : out std_logic_vector(1 downto 0);
00937       TX1P_OUT_AH         : out std_logic_vector(1 downto 0);
00938       RX_READY_FLAG_IE    : out std_logic;
00939       TX_READY_FLAG_IE    : out std_logic;
00940       RX_READY_FLAG_AH    : out std_logic;
00941       TX_READY_FLAG_AH    : out std_logic;
00942       SUM_RIS_IRENA       : out std_logic_vector(7 downto 0);
00943       SUM_FAL_IRENA       : out std_logic_vector(7 downto 0);
00944       T1_IRENA            : out std_logic_vector(7 downto 0);
00945       T2_IRENA            : out std_logic_vector(7 downto 0);
00946       T3_IRENA            : out std_logic_vector(7 downto 0);
00947       W1_IRENA            : out std_logic_vector(7 downto 0);
00948       W2_IRENA            : out std_logic_vector(7 downto 0);
00949       W3_IRENA            : out std_logic_vector(7 downto 0);
00950       STATUS_T1_IRENA     : out std_logic;
00951       STATUS_T2_IRENA     : out std_logic;
00952       STATUS_T3_IRENA     : out std_logic;
00953       STATUS_W1_IRENA     : out std_logic;
00954       STATUS_W2_IRENA     : out std_logic;
00955       STATUS_W3_IRENA     : out std_logic;
00956       OVERFLOW_IRENA      : out std_logic;
00957       SUM_RIS_EWA         : out std_logic_vector(7 downto 0);
00958       SUM_FAL_EWA         : out std_logic_vector(7 downto 0);
00959       T1_EWA              : out std_logic_vector(7 downto 0);
00960       T2_EWA              : out std_logic_vector(7 downto 0);
00961       T3_EWA              : out std_logic_vector(7 downto 0);
00962       W1_EWA              : out std_logic_vector(7 downto 0);
00963       W2_EWA              : out std_logic_vector(7 downto 0);
00964       W3_EWA              : out std_logic_vector(7 downto 0);
00965       STATUS_T1_EWA       : out std_logic;
00966       STATUS_T2_EWA       : out std_logic;
00967       STATUS_T3_EWA       : out std_logic;
00968       STATUS_W1_EWA       : out std_logic;
00969       STATUS_W2_EWA       : out std_logic;
00970       STATUS_W3_EWA       : out std_logic;
00971       OVERFLOW_EWA        : out std_logic;
00972       SUM_RIS_ANDREJ      : out std_logic_vector(7 downto 0);
00973       SUM_FAL_ANDREJ      : out std_logic_vector(7 downto 0);
00974       T1_ANDREJ           : out std_logic_vector(7 downto 0);
00975       T2_ANDREJ           : out std_logic_vector(7 downto 0);
00976       T3_ANDREJ           : out std_logic_vector(7 downto 0);
00977       W1_ANDREJ           : out std_logic_vector(7 downto 0);
00978       W2_ANDREJ           : out std_logic_vector(7 downto 0);
00979       W3_ANDREJ           : out std_logic_vector(7 downto 0);
00980       STATUS_T1_ANDREJ    : out std_logic;
00981       STATUS_T2_ANDREJ    : out std_logic;
00982       STATUS_T3_ANDREJ    : out std_logic;
00983       STATUS_W1_ANDREJ    : out std_logic;
00984       STATUS_W2_ANDREJ    : out std_logic;
00985       STATUS_W3_ANDREJ    : out std_logic;
00986       OVERFLOW_ANDREJ     : out std_logic;
00987       SUM_RIS_HEINZ       : out std_logic_vector(7 downto 0);
00988       SUM_FAL_HEINZ       : out std_logic_vector(7 downto 0);
00989       T1_HEINZ            : out std_logic_vector(7 downto 0);
00990       T2_HEINZ            : out std_logic_vector(7 downto 0);
00991       T3_HEINZ            : out std_logic_vector(7 downto 0);
00992       W1_HEINZ            : out std_logic_vector(7 downto 0);
00993       W2_HEINZ            : out std_logic_vector(7 downto 0);
00994       W3_HEINZ            : out std_logic_vector(7 downto 0);
00995       STATUS_T1_HEINZ     : out std_logic;
00996       STATUS_T2_HEINZ     : out std_logic;
00997       STATUS_T3_HEINZ     : out std_logic;
00998       STATUS_W1_HEINZ     : out std_logic;
00999       STATUS_W2_HEINZ     : out std_logic;
01000       STATUS_W3_HEINZ     : out std_logic;
01001       OVERFLOW_HEINZ      : out std_logic;
01002       MASK_IRENA          : out std_logic;
01003       MASK_EWA            : out std_logic;
01004       MASK_ANDREJ         : out std_logic;
01005       MASK_HEINZ          : out std_logic;
01006       CAL_DONE            : out std_logic;
01007       RAW_DATA_IRENA      : out std_logic_vector(31 downto 0);
01008       RAW_DATA_EWA        : out std_logic_vector(31 downto 0);
01009       RAW_DATA_ANDREJ     : out std_logic_vector(31 downto 0);
01010       RAW_DATA_HEINZ      : out std_logic_vector(31 downto 0);
01011       COARSE_TIME_IRENA   : in  std_logic_vector(7 downto 0);
01012       COARSE_TIME_EWA     : in  std_logic_vector(7 downto 0);
01013       COARSE_TIME_ANDREJ  : in  std_logic_vector(7 downto 0);
01014       COARSE_TIME_HEINZ   : in  std_logic_vector(7 downto 0);
01015       ADJUST_TIME_IRENA   : in  integer range 0 to 32 := 0;
01016       ADJUST_TIME_EWA     : in  integer range 0 to 32 := 0;
01017       ADJUST_TIME_ANDREJ  : in  integer range 0 to 32 := 0;
01018       ADJUST_TIME_HEINZ   : in  integer range 0 to 32 := 0;
01019       ADJUST_TIME_IRENA2  : in  integer range 0 to 32 := 0;
01020       ADJUST_TIME_EWA2    : in  integer range 0 to 32 := 0;
01021       ADJUST_TIME_ANDREJ2 : in  integer range 0 to 32 := 0;
01022       ADJUST_TIME_HEINZ2  : in  integer range 0 to 32 := 0
01023       );
01024   end component;
01025 
01026 
01027   component ddr2_chksum_cal
01028     port(
01029       CLK        : in  std_logic;
01030       RESET      : in  std_logic;
01031       EN         : in  std_logic;
01032       DATA_IN    : in  std_logic_vector(127 downto 0);
01033       WRITE_DONE : in  std_logic;
01034       READ_DATA  : in  std_logic;
01035       CAL_COMPL  : out std_logic;
01036       DATA_OUT   : out std_logic_vector(15 downto 0)
01037       );
01038   end component;
01039 
01040 
01041   component ddr_chksum_cal
01042     port(
01043       CLK        : in  std_logic;
01044       RESET      : in  std_logic;
01045       EN         : in  std_logic;
01046       DATA_IN    : in  std_logic_vector(63 downto 0);
01047       WRITE_DONE : in  std_logic;
01048       READ_DATA  : in  std_logic;
01049       CAL_COMPL  : out std_logic;
01050       DATA_OUT   : out std_logic_vector(15 downto 0)
01051       );
01052   end component;
01053 
01054 
01055   component sata is
01056     generic (
01057       C_SIMULATION : integer := 0
01058       );
01059     port
01060       (
01061         CLK_RIO_IN         : in  std_logic;
01062         CLK_DRP_IN         : in  std_logic;
01063         CLK_DATA_IN        : in  std_logic;
01064         USRCLK_STABLE_IN   : in  std_logic;
01065         TX_SYSTEM_RESET_IN : in  std_logic;
01066         RXP_SATA_IN        : in  std_logic_vector (1 downto 0);
01067         RXN_SATA_IN        : in  std_logic_vector (1 downto 0);
01068         TXP_SATA_OUT       : out std_logic_vector (1 downto 0);
01069         TXN_SATA_OUT       : out std_logic_vector (1 downto 0);
01070         MGTA_TXLOCK_OUT    : out std_logic;
01071         MGTA_RXLOCK_OUT    : out std_logic;
01072         MGTB_TXLOCK_OUT    : out std_logic;
01073         MGTB_RXLOCK_OUT    : out std_logic;
01074         TX_READY           : out std_logic;
01075         RX_READY           : out std_logic;
01076         DATA_IN            : in  std_logic_vector (63 downto 0);
01077         DATA_READY_IN      : in  std_logic;
01078         DATA_CONTROL_IN    : in  std_logic_vector (7 downto 0);
01079         EOP_IN             : in  std_logic;
01080         DATA_OUT           : out std_logic_vector (63 downto 0);
01081         DATA_READY_OUT     : out std_logic;
01082         DATA_CONTROL_OUT   : out std_logic_vector (7 downto 0);
01083         EOP_OUT            : out std_logic;
01084         PACKAGE_OK_OUT     : out std_logic;
01085         DATA_ERROR_OUT     : out std_logic;
01086         SCOPE_OUT          : out std_logic_vector (191 downto 0)
01087         );
01088   end component;
01089 
01090 
01091   component command_decoder
01092     port(
01093       CLOCK_IN            : in  std_logic;
01094       RESET               : in  std_logic;
01095       ADDRESS_IN          : in  std_logic_vector(11 downto 0);
01096       DATA_IN             : in  std_logic_vector(7 downto 0);
01097       DATA_VALID_IN       : in  std_logic;
01098       MODE                : out std_logic;
01099       FPGA_RESET          : out std_logic;
01100       RIO_RESET           : out std_logic_vector(7 downto 0);
01101       BUFFER_DUMP_START   : out std_logic;
01102       BUFFER_DUMP_STOP    : out std_logic;
01103       S_LINK_START        : out std_logic;
01104       S_LINK_END          : out std_logic;
01105       S_LINK_PAUSE        : out std_logic;
01106       FILL_BUFFER         : out std_logic;
01107       START_OF_RUN        : out std_logic;
01108       POST_MORTEM         : out std_logic;
01109       ADJ_TIME_0          : out integer range 0 to 64;
01110       ADJ_TIME_1          : out integer range 0 to 64;
01111       ADJ_TIME_2          : out integer range 0 to 64;
01112       ADJ_TIME_3          : out integer range 0 to 64;
01113       ADJ_TIME_4          : out integer range 0 to 64;
01114       ADJ_TIME_5          : out integer range 0 to 64;
01115       ADJ_TIME_6          : out integer range 0 to 64;
01116       ADJ_TIME_7          : out integer range 0 to 64;
01117       ADJ_TIME_PULSE      : out std_logic_vector(7 downto 0);
01118       NUMBER_OF_BUNCHES   : out integer range 0 to 127;
01119       ECR_COUNT           : out std_logic_vector(7 downto 0);
01120       L1A_COUNT           : out std_logic_vector(23 downto 0);
01121       DSS_ABORT           : out std_logic;
01122       DSS_WARNING         : out std_logic;
01123       BEAM_PERMIT         : out std_logic;
01124       INJECTION_PERMIT    : out std_logic;
01125       CTP_PATTERN         : out std_logic_vector(9 downto 1);
01126       PARAMETERS_I_PULSE  : out std_logic_vector(7 downto 0);
01127       RUN_NUMBER          : out std_logic_vector(31 downto 0);
01128       RUN_NUMBER_PULSE    : out std_logic;
01129       EVENT_TYPE          : out std_logic_vector(31 downto 0);
01130       EVENT_TYPE_PULSE    : out std_logic;
01131       BUSY_EXTERNAL       : out std_logic;
01132       SOURCE_ID           : out std_logic_vector(23 downto 0);
01133       SOURCE_ID_PULSE     : out std_logic;
01134       ALGO_SELECT         : out std_logic_vector(7 downto 0);
01135       ALGO_SELECT_PULSE   : out std_logic;
01136       PACKET_ACK          : out std_logic;
01137       RESET_COUNTERS      : out std_logic;
01138       GET_STATUS          : out std_logic;
01139       RESERVED            : out std_logic_vector(7 downto 0);
01140       INPUT_MASK          : out std_logic_vector(7 downto 0);
01141       INPUT_MASK_PULSE    : out std_logic;
01142       PACKET_OK           : out std_logic;
01143       PACKET_ERROR        : out std_logic;
01144       PACKET_MISSED       : out std_logic;
01145       FPGA_ID             : out std_logic_vector(7 downto 0);
01146       FPGA_ID_PULSE       : out std_logic;
01147       READ_TDAQ_STATUS    : out std_logic;
01148       BUSY_EXTERNAL_CLR   : out std_logic;
01149       LVL1_ACCEPT         : out std_logic_vector(5 downto 0);
01150       LVL1_ACCEPT_PULSE   : out std_logic;
01151       FORMAT_VER          : out std_logic_vector(31 downto 0);
01152       FORMAT_VER_PULSE    : out std_logic;
01153       L1TT                : out std_logic_vector(7 downto 0);
01154       L1TT_PULSE          : out std_logic;
01155       ORBIT_COUNTER       : out std_logic_vector(31 downto 0);
01156       ORBIT_COUNTER_PULSE : out std_logic;
01157       INHIBIT_DELAY       : out std_logic_vector(7 downto 0);
01158       INHIBIT_DELAY_PULSE : out std_logic;
01159       TRIGGER_DELAY       : out std_logic_vector(7 downto 0);
01160       TRIGGER_DELAY_PULSE : out std_logic;
01161       LATENCY             : out std_logic_vector(7 downto 0);
01162       LATENCY_PULSE       : out std_logic;
01163       FORCE_BCR           : out std_logic;
01164       FORCE_ECR           : out std_logic;
01165       FORCE_LVL1          : out std_logic;
01166       COARSE_DELAY_0      : out std_logic_vector(7 downto 0);
01167       COARSE_DELAY_1      : out std_logic_vector(7 downto 0);
01168       COARSE_DELAY_2      : out std_logic_vector(7 downto 0);
01169       COARSE_DELAY_3      : out std_logic_vector(7 downto 0);
01170       COARSE_DELAY_4      : out std_logic_vector(7 downto 0);
01171       COARSE_DELAY_5      : out std_logic_vector(7 downto 0);
01172       COARSE_DELAY_6      : out std_logic_vector(7 downto 0);
01173       COARSE_DELAY_7      : out std_logic_vector(7 downto 0);
01174       COARSE_DELAY_PULSE  : out std_logic_vector(7 downto 0);
01175       TTY_SOURCE          : out std_logic;
01176       TTY_SOURCE_PULSE    : out std_logic;
01177       DSSW_SOURCE         : out std_logic;
01178       DSSW_SOURCE_PULSE   : out std_logic;
01179       DSSA_SOURCE         : out std_logic;
01180       DSSA_SOURCE_PULSE   : out std_logic;
01181       CIBI_SOURCE         : out std_logic;
01182       CIBI_SOURCE_PULSE   : out std_logic;
01183       CIBB_SOURCE         : out std_logic;
01184       CIBB_SOURCE_PULSE   : out std_logic;
01185       ACK_DSSW            : out std_logic;
01186       ACK_DSSA            : out std_logic;
01187       ACK_CIBI            : out std_logic;
01188       ACK_CIBB            : out std_logic;
01189       CTP_SOURCE          : out std_logic;
01190       CTP_SOURCE_PULSE    : out std_logic;
01191       CUT_COIN_L          : out std_logic_vector(7 downto 0);
01192       CUT_COIN_H          : out std_logic_vector(7 downto 0);
01193       CUT_WIDE_L          : out std_logic_vector(7 downto 0);
01194       CUT_WIDE_H          : out std_logic_vector(7 downto 0);
01195       CUT_OUTA_L          : out std_logic_vector(7 downto 0);
01196       CUT_OUTA_H          : out std_logic_vector(7 downto 0);
01197       CUT_OUTC_L          : out std_logic_vector(7 downto 0);
01198       CUT_OUTC_H          : out std_logic_vector(7 downto 0);
01199       CUT_VLD             : out std_logic_vector(7 downto 0)
01200       );
01201   end component;
01202 
01203 
01204   component dss_comm is
01205     port (
01206       CLK           : in  std_logic;
01207       RESET         : in  std_logic;
01208       SET           : in  std_logic_vector(1 downto 0);
01209       SET_EN        : in  std_logic_vector(1 downto 0);
01210       DSS_ABORT_1   : out std_logic;
01211       DSS_ABORT_2   : out std_logic;
01212       DSS_WARNING_1 : out std_logic;
01213       DSS_WARNING_2 : out std_logic
01214       );
01215   end component;
01216 
01217 
01218   component cibu_comm is
01219     port (
01220       CLK              : in  std_logic;
01221       RESET            : in  std_logic;
01222       INJ_PERM_SET_EN  : in  std_logic;
01223       INJ_PERM_SET     : in  std_logic;
01224       BEAM_PERM_SET_EN : in  std_logic;
01225       BEAM_PERM_SET    : in  std_logic;
01226       INJ_PERM_1       : out std_logic;
01227       INJ_PERM_2       : out std_logic;
01228       BEAM_PERM_1      : out std_logic;
01229       BEAM_PERM_2      : out std_logic
01230       );
01231   end component;
01232 
01233 
01234   component ctp_comm is
01235     port (
01236       CLK     : in  std_logic;
01237       RESET   : in  std_logic;
01238       SET_EN  : in  std_logic;
01239       SET_VAL : in  std_logic_vector(9 downto 1);
01240       CTP_OUT : out std_logic_vector(9 downto 1)
01241       );
01242   end component;
01243 
01244 
01245   component raw_data_emul
01246     generic (
01247       CONF : bit_vector(1 to 8));
01248     port (
01249       CLK   : in  std_logic;
01250       RESET : in  std_logic;
01251       EN    : in  std_logic;
01252       CH1   : out std_logic_vector(31 downto 0);
01253       CH2   : out std_logic_vector(31 downto 0);
01254       CH3   : out std_logic_vector(31 downto 0);
01255       CH4   : out std_logic_vector(31 downto 0);
01256       CH5   : out std_logic_vector(31 downto 0);
01257       CH6   : out std_logic_vector(31 downto 0);
01258       CH7   : out std_logic_vector(31 downto 0);
01259       CH8   : out std_logic_vector(31 downto 0)
01260       );
01261   end component;
01262 
01263 
01264   component proc_data_emul
01265     port (
01266       CLK   : in  std_logic;
01267       RESET : in  std_logic;
01268       EN    : in  std_logic;
01269       CH1   : out std_logic_vector(23 downto 0);
01270       CH2   : out std_logic_vector(23 downto 0);
01271       CH3   : out std_logic_vector(23 downto 0);
01272       CH4   : out std_logic_vector(23 downto 0);
01273       CH5   : out std_logic_vector(23 downto 0);
01274       CH6   : out std_logic_vector(23 downto 0);
01275       CH7   : out std_logic_vector(23 downto 0);
01276       CH8   : out std_logic_vector(23 downto 0)
01277       );
01278   end component;
01279 
01280 
01281   component status_collector
01282     port(
01283       DEBUG           : out std_logic_vector(14 downto 0);
01284       EMAC_CLK        : in  std_logic;
01285       RATES_CLK       : in  std_logic;
01286       STATUS_CLK      : in  std_logic;
01287       RIO_CLK         : in  std_logic;
01288       RESET           : in  std_logic;
01289       START           : in  std_logic;
01290       FETCH_BYTE      : in  std_logic;
01291       FETCH_CHKSUM    : in  std_logic;
01292       ERROR_FLAG      : in  std_logic;
01293       EXT_CLK_DET     : in  std_logic;
01294       RIO_DAQ         : in  std_logic;
01295       RIO_SATA        : in  std_logic;
01296       MODE            : in  std_logic;
01297       DCM_STATUS      : in  std_logic;
01298       ROD_STATUS      : in  std_logic;
01299       MAIN_FSM        : in  std_logic_vector(7 downto 0);
01300       FPGA_ID         : in  std_logic_vector(7 downto 0)   := x"00";
01301       DSS_CIBU_STATUS : in  std_logic_vector(31 downto 0);
01302       ERROR_CODE      : in  std_logic_vector(31 downto 0);
01303       INPUT_STATUS    : in  std_logic_vector(63 downto 0);
01304       TDAQ_PARAMS     : in  std_logic_vector(159 downto 0) := (others => '0');
01305       HITRATE_CH1     : in  std_logic_vector(31 downto 0)  := (others => '0');
01306       HITRATE_CH2     : in  std_logic_vector(31 downto 0)  := (others => '0');
01307       HITRATE_CH3     : in  std_logic_vector(31 downto 0)  := (others => '0');
01308       HITRATE_CH4     : in  std_logic_vector(31 downto 0)  := (others => '0');
01309       HITRATE_CH5     : in  std_logic_vector(31 downto 0)  := (others => '0');
01310       HITRATE_CH6     : in  std_logic_vector(31 downto 0)  := (others => '0');
01311       HITRATE_CH7     : in  std_logic_vector(31 downto 0)  := (others => '0');
01312       HITRATE_CH8     : in  std_logic_vector(31 downto 0)  := (others => '0');
01313       ALGO_STATE      : in  std_logic_vector(31 downto 0);
01314       HITRATE_A_CH1   : in  std_logic_vector(31 downto 0)  := (others => '0');
01315       HITRATE_A_CH2   : in  std_logic_vector(31 downto 0)  := (others => '0');
01316       HITRATE_A_CH3   : in  std_logic_vector(31 downto 0)  := (others => '0');
01317       HITRATE_A_CH4   : in  std_logic_vector(31 downto 0)  := (others => '0');
01318       HITRATE_A_CH5   : in  std_logic_vector(31 downto 0)  := (others => '0');
01319       HITRATE_A_CH6   : in  std_logic_vector(31 downto 0)  := (others => '0');
01320       HITRATE_A_CH7   : in  std_logic_vector(31 downto 0)  := (others => '0');
01321       HITRATE_A_CH8   : in  std_logic_vector(31 downto 0)  := (others => '0');
01322       HITRATE_B_CH1   : in  std_logic_vector(31 downto 0)  := (others => '0');
01323       HITRATE_B_CH2   : in  std_logic_vector(31 downto 0)  := (others => '0');
01324       HITRATE_B_CH3   : in  std_logic_vector(31 downto 0)  := (others => '0');
01325       HITRATE_B_CH4   : in  std_logic_vector(31 downto 0)  := (others => '0');
01326       HITRATE_B_CH5   : in  std_logic_vector(31 downto 0)  := (others => '0');
01327       HITRATE_B_CH6   : in  std_logic_vector(31 downto 0)  := (others => '0');
01328       HITRATE_B_CH7   : in  std_logic_vector(31 downto 0)  := (others => '0');
01329       HITRATE_B_CH8   : in  std_logic_vector(31 downto 0)  := (others => '0');
01330       HITRATE_C_CH1   : in  std_logic_vector(31 downto 0)  := (others => '0');
01331       HITRATE_C_CH2   : in  std_logic_vector(31 downto 0)  := (others => '0');
01332       HITRATE_C_CH3   : in  std_logic_vector(31 downto 0)  := (others => '0');
01333       HITRATE_C_CH4   : in  std_logic_vector(31 downto 0)  := (others => '0');
01334       HITRATE_C_CH5   : in  std_logic_vector(31 downto 0)  := (others => '0');
01335       HITRATE_C_CH6   : in  std_logic_vector(31 downto 0)  := (others => '0');
01336       HITRATE_C_CH7   : in  std_logic_vector(31 downto 0)  := (others => '0');
01337       HITRATE_C_CH8   : in  std_logic_vector(31 downto 0)  := (others => '0');
01338       HITRATE_D_CH1   : in  std_logic_vector(31 downto 0)  := (others => '0');
01339       HITRATE_D_CH2   : in  std_logic_vector(31 downto 0)  := (others => '0');
01340       HITRATE_D_CH3   : in  std_logic_vector(31 downto 0)  := (others => '0');
01341       HITRATE_D_CH4   : in  std_logic_vector(31 downto 0)  := (others => '0');
01342       HITRATE_D_CH5   : in  std_logic_vector(31 downto 0)  := (others => '0');
01343       HITRATE_D_CH6   : in  std_logic_vector(31 downto 0)  := (others => '0');
01344       HITRATE_D_CH7   : in  std_logic_vector(31 downto 0)  := (others => '0');
01345       HITRATE_D_CH8   : in  std_logic_vector(31 downto 0)  := (others => '0');
01346       ASM_DONE        : out std_logic;
01347       TRANS_DONE      : out std_logic;
01348       CHKSUM_OUT      : out std_logic_vector(15 downto 0);
01349       DATA_OUT        : out std_logic_vector(7 downto 0)
01350       );
01351   end component;
01352 
01353 
01354   component tdaq_collector
01355     port(
01356       EMAC_CLK            : in  std_logic;
01357       ROD_CLK             : in  std_logic;
01358       STATUS_CLK          : in  std_logic;
01359       RIO_CLK             : in  std_logic;
01360       RESET               : in  std_logic;
01361       START               : in  std_logic;
01362       FETCH_BYTE          : in  std_logic;
01363       FETCH_CHKSUM        : in  std_logic;
01364       FPGA_ID             : in  std_logic_vector(7 downto 0);
01365       ERROR_CODE          : in  std_logic_vector(7 downto 0);
01366       INPUT_STATUS        : in  std_logic_vector(63 downto 0);
01367       DATA_SRC            : in  std_logic_vector(7 downto 0);
01368       COARSE_DELAY1       : in  std_logic_vector(7 downto 0);
01369       COARSE_DELAY2       : in  std_logic_vector(7 downto 0);
01370       COARSE_DELAY3       : in  std_logic_vector(7 downto 0);
01371       COARSE_DELAY4       : in  std_logic_vector(7 downto 0);
01372       COARSE_DELAY5       : in  std_logic_vector(7 downto 0);
01373       COARSE_DELAY6       : in  std_logic_vector(7 downto 0);
01374       COARSE_DELAY7       : in  std_logic_vector(7 downto 0);
01375       COARSE_DELAY8       : in  std_logic_vector(7 downto 0);
01376       FINE_DELAY1         : in  std_logic_vector(7 downto 0);
01377       FINE_DELAY2         : in  std_logic_vector(7 downto 0);
01378       FINE_DELAY3         : in  std_logic_vector(7 downto 0);
01379       FINE_DELAY4         : in  std_logic_vector(7 downto 0);
01380       FINE_DELAY5         : in  std_logic_vector(7 downto 0);
01381       FINE_DELAY6         : in  std_logic_vector(7 downto 0);
01382       FINE_DELAY7         : in  std_logic_vector(7 downto 0);
01383       FINE_DELAY8         : in  std_logic_vector(7 downto 0);
01384       BUSY                : in  std_logic_vector(7 downto 0);
01385       BUSY_EXT            : in  std_logic_vector(7 downto 0);
01386       SLINK_FULL          : in  std_logic_vector(7 downto 0);
01387       SLINK_DOWN          : in  std_logic_vector(7 downto 0);
01388       L1A                 : in  std_logic;
01389       L1A_FIFO_FULL       : in  std_logic;
01390       L1A_FIFO_EMPTY      : in  std_logic;
01391       TRIGGER_DELAY       : in  std_logic_vector(7 downto 0);
01392       EXT_EVENT_ID        : in  std_logic_vector(31 downto 0);
01393       ORBIT_ID            : in  std_logic_vector(31 downto 0);
01394       INHIBIT_DELAY       : in  std_logic_vector(7 downto 0);
01395       BCID                : in  std_logic_vector(31 downto 0);
01396       DETECTOR_EVENT_TYPE : in  std_logic_vector(31 downto 0);
01397       SOURCE_ID           : in  std_logic_vector(31 downto 0);
01398       FORMAT_V            : in  std_logic_vector(31 downto 0);
01399       RUN_NUMBER          : in  std_logic_vector(31 downto 0);
01400       TRIGGER_TYPE        : in  std_logic_vector(7 downto 0);
01401       CTP_OUT             : in  std_logic_vector(8 downto 0);
01402       CTP_FORCE           : in  std_logic_vector(8 downto 0);
01403       CTP_SEL             : in  std_logic_vector(7 downto 0);
01404       DSS_WARNING         : in  std_logic;
01405       DSS_ABORT           : in  std_logic;
01406       INJ_PERM            : in  std_logic;
01407       BEAM_PERM           : in  std_logic;
01408       NUM_BUNCH           : in  std_logic_vector(7 downto 0);
01409       TTY_SEL             : in  std_logic_vector(7 downto 0);
01410       DSSA_SEL            : in  std_logic_vector(7 downto 0);
01411       DSSW_SEL            : in  std_logic_vector(7 downto 0);
01412       CIBI_SEL            : in  std_logic_vector(7 downto 0);
01413       CIBB_SEL            : in  std_logic_vector(7 downto 0);
01414       RX_LOCK             : in  std_logic_vector(7 downto 0);
01415       TX_LOCK             : in  std_logic_vector(7 downto 0);
01416       RX_READY            : in  std_logic_vector(7 downto 0);
01417       TX_READY            : in  std_logic_vector(7 downto 0);
01418       LATENCY             : in  std_logic_vector(7 downto 0);
01419       CUT_COIN_L          : in  std_logic_vector(7 downto 0);
01420       CUT_COIN_H          : in  std_logic_vector(7 downto 0);
01421       CUT_WIDE_L          : in  std_logic_vector(7 downto 0);
01422       CUT_WIDE_H          : in  std_logic_vector(7 downto 0);
01423       CUT_OUTA_L          : in  std_logic_vector(7 downto 0);
01424       CUT_OUTA_H          : in  std_logic_vector(7 downto 0);
01425       CUT_OUTC_L          : in  std_logic_vector(7 downto 0);
01426       CUT_OUTC_H          : in  std_logic_vector(7 downto 0);
01427       TRATE_AttC          : in  std_logic_vector(31 downto 0);
01428       TRATE_AttA          : in  std_logic_vector(31 downto 0);
01429       TRATE_Mult3pC       : in  std_logic_vector(31 downto 0);
01430       TRATE_Mult2C        : in  std_logic_vector(31 downto 0);
01431       TRATE_Mult1C        : in  std_logic_vector(31 downto 0);
01432       TRATE_Mult3pA       : in  std_logic_vector(31 downto 0);
01433       TRATE_Mult2A        : in  std_logic_vector(31 downto 0);
01434       TRATE_Mult1A        : in  std_logic_vector(31 downto 0);
01435       TRATE_Wide          : in  std_logic_vector(31 downto 0);
01436       TRATE_CtoA          : in  std_logic_vector(31 downto 0);
01437       TRATE_AtoC          : in  std_logic_vector(31 downto 0);
01438       TRANS_DONE          : out std_logic;
01439       ASM_DONE            : out std_logic;
01440       CHKSUM_OUT          : out std_logic_vector(15 downto 0);
01441       DATA_OUT            : out std_logic_vector(7 downto 0)
01442       );
01443   end component;
01444 
01445 
01446   component statistics
01447     generic (
01448       SERIES_LENGTH : integer);
01449     port(
01450       CLK : in  std_logic;
01451       RES : in  std_logic;
01452       VAL : in  std_logic_vector(15 downto 0);
01453       MNM : out std_logic_vector(15 downto 0);
01454       MAX : out std_logic_vector(15 downto 0);
01455       AVG : out std_logic_vector(15 downto 0)
01456       );
01457   end component;
01458 
01459 
01460   component ctp_logic
01461     port(
01462       CLK              : in  std_logic;
01463       UPPER_BOUND_A    : in  std_logic_vector(5 downto 0) := "101110";
01464       LOWER_BOUND_A    : in  std_logic_vector(5 downto 0) := "010000";
01465       UPPER_BOUND_C    : in  std_logic_vector(5 downto 0) := "101110";
01466       LOWER_BOUND_C    : in  std_logic_vector(5 downto 0) := "010000";
01467       UPPER_BOUND_A1   : in  std_logic_vector(5 downto 0) := "101110";
01468       LOWER_BOUND_A1   : in  std_logic_vector(5 downto 0) := "010000";
01469       UPPER_BOUND_C1   : in  std_logic_vector(5 downto 0) := "101110";
01470       LOWER_BOUND_C1   : in  std_logic_vector(5 downto 0) := "010000";
01471       UPPER_BOUND_AW   : in  std_logic_vector(5 downto 0) := "111111";
01472       LOWER_BOUND_AW   : in  std_logic_vector(5 downto 0) := "000001";
01473       UPPER_BOUND_CW   : in  std_logic_vector(5 downto 0) := "111111";
01474       LOWER_BOUND_CW   : in  std_logic_vector(5 downto 0) := "000001";
01475       IRENA1           : in  std_logic_vector(7 downto 0);
01476       EWA1             : in  std_logic_vector(7 downto 0);
01477       HEINZ1           : in  std_logic_vector(7 downto 0);
01478       ANDREJ1          : in  std_logic_vector(7 downto 0);
01479       MARKO1           : in  std_logic_vector(7 downto 0);
01480       WILLIAM1         : in  std_logic_vector(7 downto 0);
01481       HARRIS1          : in  std_logic_vector(7 downto 0);
01482       HELMUT1          : in  std_logic_vector(7 downto 0);
01483       IRENA2           : in  std_logic_vector(7 downto 0);
01484       EWA2             : in  std_logic_vector(7 downto 0);
01485       HEINZ2           : in  std_logic_vector(7 downto 0);
01486       ANDREJ2          : in  std_logic_vector(7 downto 0);
01487       MARKO2           : in  std_logic_vector(7 downto 0);
01488       WILLIAM2         : in  std_logic_vector(7 downto 0);
01489       HARRIS2          : in  std_logic_vector(7 downto 0);
01490       HELMUT2          : in  std_logic_vector(7 downto 0);
01491       S_IRENA1         : in  std_logic;
01492       S_EWA1           : in  std_logic;
01493       S_HEINZ1         : in  std_logic;
01494       S_ANDREJ1        : in  std_logic;
01495       S_MARKO1         : in  std_logic;
01496       S_WILLIAM1       : in  std_logic;
01497       S_HARRIS1        : in  std_logic;
01498       S_HELMUT1        : in  std_logic;
01499       S_IRENA2         : in  std_logic;
01500       S_EWA2           : in  std_logic;
01501       S_HEINZ2         : in  std_logic;
01502       S_ANDREJ2        : in  std_logic;
01503       S_MARKO2         : in  std_logic;
01504       S_WILLIAM2       : in  std_logic;
01505       S_HARRIS2        : in  std_logic;
01506       S_HELMUT2        : in  std_logic;
01507       OTHER_IRENA1     : in  std_logic_vector(7 downto 0) := "00000000";
01508       OTHER_EWA1       : in  std_logic_vector(7 downto 0) := "00000000";
01509       OTHER_HEINZ1     : in  std_logic_vector(7 downto 0) := "00000000";
01510       OTHER_ANDREJ1    : in  std_logic_vector(7 downto 0) := "00000000";
01511       OTHER_MARKO1     : in  std_logic_vector(7 downto 0) := "00000000";
01512       OTHER_WILLIAM1   : in  std_logic_vector(7 downto 0) := "00000000";
01513       OTHER_HARRIS1    : in  std_logic_vector(7 downto 0) := "00000000";
01514       OTHER_HELMUT1    : in  std_logic_vector(7 downto 0) := "00000000";
01515       OTHER_IRENA2     : in  std_logic_vector(7 downto 0) := "00000000";
01516       OTHER_EWA2       : in  std_logic_vector(7 downto 0) := "00000000";
01517       OTHER_HEINZ2     : in  std_logic_vector(7 downto 0) := "00000000";
01518       OTHER_ANDREJ2    : in  std_logic_vector(7 downto 0) := "00000000";
01519       OTHER_MARKO2     : in  std_logic_vector(7 downto 0) := "00000000";
01520       OTHER_WILLIAM2   : in  std_logic_vector(7 downto 0) := "00000000";
01521       OTHER_HARRIS2    : in  std_logic_vector(7 downto 0) := "00000000";
01522       OTHER_HELMUT2    : in  std_logic_vector(7 downto 0) := "00000000";
01523       OTHER_S_IRENA1   : in  std_logic                    := '0';
01524       OTHER_S_EWA1     : in  std_logic                    := '0';
01525       OTHER_S_HEINZ1   : in  std_logic                    := '0';
01526       OTHER_S_ANDREJ1  : in  std_logic                    := '0';
01527       OTHER_S_MARKO1   : in  std_logic                    := '0';
01528       OTHER_S_WILLIAM1 : in  std_logic                    := '0';
01529       OTHER_S_HARRIS1  : in  std_logic                    := '0';
01530       OTHER_S_HELMUT1  : in  std_logic                    := '0';
01531       OTHER_S_IRENA2   : in  std_logic                    := '0';
01532       OTHER_S_EWA2     : in  std_logic                    := '0';
01533       OTHER_S_HEINZ2   : in  std_logic                    := '0';
01534       OTHER_S_ANDREJ2  : in  std_logic                    := '0';
01535       OTHER_S_MARKO2   : in  std_logic                    := '0';
01536       OTHER_S_WILLIAM2 : in  std_logic                    := '0';
01537       OTHER_S_HARRIS2  : in  std_logic                    := '0';
01538       OTHER_S_HELMUT2  : in  std_logic                    := '0';
01539       CTP_OUT          : out std_logic_vector(9 downto 1)
01540       );
01541   end component;
01542 
01543 
01544   component bcm_signal_delay
01545     port(
01546       CLK           : in  std_logic;
01547       SCLR          : in  std_logic;
01548       DELAY_SETTING : in  std_logic_vector(7 downto 0);
01549       DATA_INPUT    : in  std_logic;
01550       DATA_OUTPUT   : out std_logic
01551       );
01552   end component;
01553 
01554 
01555   component bcm_signal_delay_vec
01556     port(
01557       CLK           : in  std_logic;
01558       SCLR          : in  std_logic;
01559       delay_setting : in  std_logic_vector(7 downto 0);
01560       data_input    : in  std_logic_vector(31 downto 0);
01561       data_output   : out std_logic_vector(31 downto 0)
01562       );
01563   end component;
01564 
01565 
01566   component incrementer
01567     port(
01568       CLK      : in  std_logic;
01569       RES      : in  std_logic;
01570       INC_1    : in  std_logic;
01571       INC_2    : in  std_logic;
01572       READ_OUT : in  std_logic;
01573       VALUE    : out std_logic_vector(31 downto 0)
01574       );
01575   end component;
01576 
01577 
01578   component bridge
01579     port(
01580       CLK_RIO_IN       : in  std_logic;
01581       CLK_DRP_IN       : in  std_logic;
01582       CLK_SATA_IN      : in  std_logic;
01583       USRCLK_STABLE_IN : in  std_logic;
01584       CLK_DATA_IN      : in  std_logic;
01585       RESET_A_IN       : in  std_logic;
01586       RESET_B_IN       : in  std_logic;
01587       RXP_SATA_IN      : in  std_logic_vector(1 downto 0);
01588       RXN_SATA_IN      : in  std_logic_vector(1 downto 0);
01589       A_DATA_IN        : in  std_logic_vector(63 downto 0);
01590       B_DATA_IN        : in  std_logic_vector(63 downto 0);
01591       A_DATA_VALID_IN  : in  std_logic;
01592       B_DATA_VALID_IN  : in  std_logic;
01593       TXP_SATA_OUT     : out std_logic_vector(1 downto 0);
01594       TXN_SATA_OUT     : out std_logic_vector(1 downto 0);
01595       TX_A_READY       : out std_logic;
01596       TX_B_READY       : out std_logic;
01597       RX_A_READY       : out std_logic;
01598       RX_B_READY       : out std_logic;
01599       A_DATA_OUT       : out std_logic_vector(63 downto 0);
01600       B_DATA_OUT       : out std_logic_vector(63 downto 0);
01601       A_DATA_VALID_OUT : out std_logic;
01602       B_DATA_VALID_OUT : out std_logic;
01603       A_DATA_ERROR     : out std_logic;
01604       B_DATA_ERROR     : out std_logic;
01605       A_LISTENING      : out std_logic;
01606       B_LISTENING      : out std_logic;
01607       A_PACKAGE_GOOD   : out std_logic;
01608       B_PACKAGE_GOOD   : out std_logic;
01609       A_PACKAGE_BAD    : out std_logic;
01610       B_PACKAGE_BAD    : out std_logic;
01611       c_scope          : out std_logic_vector(165 downto 0)
01612       );
01613   end component;
01614 
01615 
01616   component abort_controller is
01617     
01618     port (
01619       CLK         : in  std_logic;
01620       RES         : in  std_logic;
01621       WR_EN       : in  std_logic;
01622       BCID        : in  std_logic_vector(11 downto 0);
01623       HIGH_GAIN   : in  std_logic_vector(3 downto 0);
01624       LOW_GAIN    : in  std_logic_vector(3 downto 0);
01625       CHECK_EN    : in  std_logic;
01626       BCID_R      : in  std_logic_vector(11 downto 0);
01627       HIGH_GAIN_R : in  std_logic_vector(3 downto 0);
01628       LOW_GAIN_R  : in  std_logic_vector(3 downto 0);
01629       ABORT       : out std_logic
01630       );
01631   end component;
01632 
01633 
01634   component BID_cnt
01635     port (
01636       BC    : in  std_logic;
01637       BCR   : in  std_logic;
01638       RESET : in  std_logic;
01639       BID   : out std_logic_vector(11 downto 0));
01640   end component;
01641 
01642 
01643   component pmdelay is
01644     generic (
01645       LAYOFF : integer range 0 to 254 := 10);
01646     port (
01647       CLK    : in  std_logic;
01648       RES    : in  std_logic;
01649       PM_IN  : in  std_logic;
01650       ORBIT  : in  std_logic;
01651       PM_OUT : out std_logic
01652       );
01653   end component;
01654 
01655 
01656   component generic_shift_reg
01657     generic (
01658       WIDTH : positive range 1 to 255;
01659       DEPTH : positive range 1 to 255);
01660     port (
01661       CLK  : in  std_logic;
01662       RES  : in  std_logic;
01663       DIN  : in  std_logic_vector(WIDTH-1 downto 0);
01664       DOUT : out std_logic_vector(WIDTH-1 downto 0)
01665       );
01666   end component;
01667 
01668 end main_components;