ddr2_mem_parameters_0.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr2/ddr2_mem_parameters_0.vhd,v $
--*  $Revision: 1.4.2.4 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:44 $                              *


--*                                                            *
--**************************************************************
-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  / Vendor: Xilinx
-- \   \   \/ Version: 1.6
--  \   \ Application : MIG
--  /   / Filename: ddr2_mem_parameters_0.vhd
-- /___/   /\ Date Last Modified:  Wed Jun 1 2005
-- \   \  /  \Date Created: Mon May 2 2005
--  \___\/\___\
-- Device: Virtex-4
-- Design Name: DDR2_SDRAM
-------------------------------------------------------------------------------


library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;










package ddr2_mem_parameters_0 is

-------------------------------------------------------------------------------
--                                constants
-------------------------------------------------------------------------------
  
  constant data_width             : integer                       := 64;
  constant data_strobe_width      : integer                       := 8;
  constant data_mask_width        : integer                       := 8;
  constant clk_width              : integer                       := 1;
  constant fifo                   : integer                       := 4;
  constant ecc_cntrl_bits         : integer                       := 0;
  constant ReadEnable             : integer                       := 3;
  constant cs_width               : integer                       := 1;
  constant odt_width              : integer                       := 1;
  constant cke_width              : integer                       := 1;
  constant deep_memory            : integer                       := 1;
  constant row_address            : integer                       := 14;
  constant column_address         : integer                       := 10;
  constant bank_address           : integer                       := 2;
  constant memory_width           : integer                       := 8;
  constant registered             : integer                       := 1;
  constant unbuffered             : integer                       := 0;
  constant col_ap_width           : integer                       := 11;
  constant DatabitsPerStrobe      : integer                       := 8;
  constant DatabitsPerMask        : integer                       := 8;
  constant no_of_CS               : integer                       := 1;
  constant RESET                  : integer                       := 1;
  constant data_mask              : integer                       := 1;
  constant ecc_enable             : integer                       := 0;
  constant ecc_disable            : integer                       := 1;
  constant ecc_width              : integer                       := 0;
  constant dq_width               : integer                       := 64;
  constant dm_width               : integer                       := 8;
  constant tb_enable              : integer                       := 0;
  constant tb_disable             : integer                       := 1;
  constant dcm_enable             : integer                       := 1;
  constant dcm_disable            : integer                       := 0;
  constant low_frequency          : integer                       := 0;
  constant high_frequency         : integer                       := 1;
  constant foundation_ise         : integer                       := 1;
  constant Data8PerReadEnable     : integer                       := 1;
  constant Data4PerReadEnable     : integer                       := 0;
  constant burst_length           : std_logic_vector(2 downto 0)  := "011";
  constant burst_type             : std_logic                     := '0';
  constant cas_latency_value      : std_logic_vector(2 downto 0)  := "100";
  constant mode                   : std_logic                     := '0';
  constant dll_rst                : std_logic                     := '0';
  constant write_recovery         : std_logic_vector(2 downto 0)  := "010";
  constant pd_mode                : std_logic                     := '0';
  constant load_mode_register     : std_logic_vector(13 downto 0) := "00010001000011";
  constant output                 : std_logic                     := '0';
  constant rdqs_ena               : std_logic                     := '0';
  constant dqs_n_ena              : std_logic                     := '0';
  constant ocd_operation          : std_logic_vector(2 downto 0)  := "000";
  constant odt_enable             : std_logic_vector(1 downto 0)  := "00";
  constant additive_latency_value : std_logic_vector(2 downto 0)  := "010";
  constant dll_ena                : std_logic                     := '0';
  constant op_drive_strength      : std_logic                     := '0';
  constant ext_load_mode_register : std_logic_vector(13 downto 0) := "00000000010000";
  constant chip_address           : integer                       := 1;
  constant rcd_count_value        : std_logic_vector(2 downto 0)  := "010";
  constant ras_count_value        : std_logic_vector(3 downto 0)  := "0111";
  constant mrd_count_value        : std_logic                     := '1';
  constant rp_count_value         : std_logic_vector(2 downto 0)  := "010";
  constant rfc_count_value        : std_logic_vector(5 downto 0)  := "001110";
  constant trtp_count_value       : std_logic_vector(2 downto 0)  := "001";
  constant twr_count_value        : std_logic_vector(2 downto 0)  := "011";
  constant twtr_count_value       : std_logic_vector(2 downto 0)  := "001";
  constant max_ref_width          : integer                       := 7;
  constant max_ref_cnt            : std_logic_vector(6 downto 0)  := "1011111";
  constant Phy_Mode               : std_logic                     := '1';
  constant cs_h0                  : std_logic_vector(3 downto 0)  := "0000";
  constant cs_h1                  : std_logic_vector(3 downto 0)  := "0001";
  constant cs_h2                  : std_logic_vector(3 downto 0)  := "0010";
  constant cs_h3                  : std_logic_vector(3 downto 0)  := "0011";
  constant cs_h5                  : std_logic_vector(3 downto 0)  := "0101";
  constant cs_h6                  : std_logic_vector(3 downto 0)  := "0110";
  constant cs_h7                  : std_logic_vector(3 downto 0)  := "0111";
  constant cs_hA                  : std_logic_vector(3 downto 0)  := "1010";
  constant cs_hB                  : std_logic_vector(3 downto 0)  := "1011";
  constant cs_hD                  : std_logic_vector(3 downto 0)  := "1101";
  constant cs_hE                  : std_logic_vector(3 downto 0)  := "1110";
  constant cs_hF                  : std_logic_vector(3 downto 0)  := "1111";
  constant cs_D100                : std_logic_vector(7 downto 0)  := X"64";
  constant cs_D1000               : std_logic_vector(11 downto 0) := X"3E8";
  constant add_const1             : std_logic_vector(15 downto 0) := X"0100";
  constant add_const2             : std_logic_vector(15 downto 0) := X"0380";
  constant add_const3             : std_logic_vector(15 downto 0) := X"0000";
  constant add_const4             : std_logic_vector(15 downto 0) := X"FBFF";
  constant add_const5             : std_logic_vector(15 downto 0) := X"FFFF";

-------------------------------------------------------------------------------
--                                typedefs
-------------------------------------------------------------------------------


  type STATE_MACHINE1 is (rise_idle, rise_first_data, rise_second_data, rise_comp_over);

  type STATE_MACHINE2 is (fall_idle, fall_first_data, fall_second_data, fall_comp_over);

end package ddr2_mem_parameters_0;

---

Author: M.Niegl

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