cibu_comm.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/div/cibu_comm.vhd,v $
--*  $Revision: 1.2.2.3 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:45 $                              *


--*                                                            *
--**************************************************************


library ieee;

use ieee.std_logic_1164.all;





entity cibu_comm is
  
  port (
    CLK              : in  std_logic;
    RESET            : in  std_logic;
    INJ_PERM_SET_EN  : in  std_logic;
    INJ_PERM_SET     : in  std_logic;
    BEAM_PERM_SET_EN : in  std_logic;
    BEAM_PERM_SET    : in  std_logic;
    INJ_PERM_1       : out std_logic;
    INJ_PERM_2       : out std_logic;
    BEAM_PERM_1      : out std_logic;
    BEAM_PERM_2      : out std_logic
    );

end cibu_comm;





architecture cibu_comm_arc of cibu_comm is

begin  -- cibu_comm_arc


  inj_set : process (CLK, RESET)
  begin  -- process inj_set
    if RESET = '1' then                 -- asynchronous reset (active high)
      INJ_PERM_1 <= '1';
      INJ_PERM_2 <= '1';
    elsif CLK'event and CLK = '1' then  -- rising clock edge
      if INJ_PERM_SET_EN = '1' then
        INJ_PERM_1 <= INJ_PERM_SET;
        INJ_PERM_2 <= INJ_PERM_SET;
      end if;
    end if;
  end process inj_set;


  beam_set : process (CLK, RESET)
  begin  -- process beam_set
    if RESET = '1' then                 -- asynchronous reset (active high)
      BEAM_PERM_1 <= '1';
      BEAM_PERM_2 <= '1';
    elsif CLK'event and CLK = '1' then  -- rising clock edge
      if BEAM_PERM_SET_EN = '1' then
        BEAM_PERM_1 <= BEAM_PERM_SET;
        BEAM_PERM_2 <= BEAM_PERM_SET;
      end if;
    end if;
  end process beam_set;

end cibu_comm_arc;

---

Author: M.Niegl

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