cnt_ddr_rd.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr/cnt_ddr_rd.vhd,v $
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:43 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;


entity cnt_ddr_rd is
  port (
    RESET : in  std_logic;
    CLK   : in  std_logic;
    EN    : in  std_logic;
    DONE  : out std_logic
    );


  attribute use_dsp48 : string;

  attribute use_dsp48 of cnt_ddr_rd  : entity is "yes";
  
end cnt_ddr_rd;


architecture cnt_ddr_rd_arc of cnt_ddr_rd is

  signal cnt    : std_logic_vector(22 downto 0) := (others => '0');
  signal done_i : std_logic                     := '0';

begin

  DONE <= done_i;


  cnt_rds : process(CLK)
  begin
    if CLK'event and CLK = '1' then
      if RESET = '1' then
        cnt    <= (others => '0');
        done_i <= '0';
      else
        if cnt = "11111111111111111111111" then
          done_i <= '1';
          cnt    <= (others => '0');
        else
          done_i <= '0';
        end if;
        if (EN = '1' and done_i = '0') then
          cnt <= cnt + 1;
        else
          cnt <= cnt;
        end if;
      end if;
    end if;
  end process cnt_rds;
end cnt_ddr_rd_arc;

---

Author: M.Niegl

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