mem_interface_top_tap_logic_0.vhd

--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr/mem_interface_top_tap_logic_0.vhd,v $                                                  *
--*  $Revision: 1.3.2.3 $                                                *
--*  $Name: dev $                                                    *
--*  $Author: mniegl $                                                  *
--*  $Date: 2008/11/03 17:57:44 $                                                    *
--*                                                            *
--**************************************************************
-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  / Vendor: Xilinx
-- \   \   \/ Version: 1.6
--  \   \ Application : MIG
--  /   / Filename: mem_interface_top_tap_logic_0.vhd
-- /___/   /\ Date Last Modified:  Wed Jun 1 2005
-- \   \  /  \Date Created: Mon May 2 2005
--  \___\/\___\
-- Device: Virtex-4
-- Design Name: DDR1_SDRAM
-- Description: Instantiates the tap_cntrl and the data_tap_inc modules. Used for 
--              calibration of the memory data with the FPGA clock.
-------------------------------------------------------------------------------


library ieee;

use ieee.std_logic_1164.all;

library unisim;

use unisim.vcomponents.all;
use work.mem_interface_top_parameters_0.all;

entity mem_interface_top_tap_logic_0 is
        port( CLK                   : in std_logic; 
              CAL_CLK               : in std_logic; 
              RESET0                : in std_logic; 
              RESET_CAL_CLK         : in std_logic; 
              idelay_ctrl_rdy       : in std_logic; 
              CTRL_DUMMYREAD_START  : in std_logic; 
              dqs_delayed           : in std_logic_vector((data_strobe_width-1) downto 0); 
              SEL_DONE              : out std_logic;
              data_idelay_inc       : out std_logic_vector((ReadEnable-1) downto 0);
              data_idelay_ce        : out std_logic_vector((ReadEnable-1) downto 0);
              data_idelay_rst       : out std_logic_vector((ReadEnable-1) downto 0);
              dqs_idelay_inc        : out std_logic_vector((ReadEnable-1) downto 0);
              dqs_idelay_ce         : out std_logic_vector((ReadEnable-1) downto 0);
              dqs_idelay_rst        : out std_logic_vector((ReadEnable-1) downto 0)
            );
end mem_interface_top_tap_logic_0;

architecture arch of mem_interface_top_tap_logic_0 is

component mem_interface_top_tap_ctrl
        port( CLK                       : in std_logic;              
              RESET                     : in std_logic;
              RDY_STATUS                : in std_logic;
              DQS                       : in std_logic;
              CTRL_DUMMYREAD_START      : in std_logic;
              DLYINC                    : out std_logic;
              DLYCE                     : out std_logic;
              DLYRST                    : out std_logic;
              SEL_DONE                  : out std_logic;
              VALID_DATA_TAP_COUNT      : out std_logic;
              DATA_TAP_COUNT            : out std_logic_vector(5 downto 0)
           );
end component;

component mem_interface_top_data_tap_inc 
        port(       
                CLK                     : in std_logic;
                RESET                   : in std_logic;
                DATA_DLYINC             : out std_logic;
                DATA_DLYCE              : out std_logic;
                DATA_DLYRST             : out std_logic;
                DATA_TAP_SEL_DONE       : out std_logic;
                DQS_sel_done            : in std_logic;
                VALID_DATA_TAP_COUNT    : in std_logic;
                DATA_TAP_COUNT          : in std_logic_vector(5 downto 0)
             );
end component;

signal data_tap_select          : std_logic_vector((ReadEnable-1) downto 0);  
signal dqs_tap_sel_done         : std_logic_vector((ReadEnable-1) downto 0); 
signal valid_tap_count          : std_logic_vector((ReadEnable-1) downto 0);  
signal data_tap_inc_done        : std_logic;
signal tap_sel_done             : std_logic;     

signal data_tap_count0  : std_logic_vector(5 downto 0);  


begin

-- For controller to stop dummy reads
SEL_DONE <= tap_sel_done;



process(CLK)
begin
 if(CLK'event and CLK = '1') then
  if (RESET0 = '1') then
        data_tap_inc_done  <= '0';
        tap_sel_done       <= '0';
  else
        data_tap_inc_done   <=  data_tap_select(0) ; --(&data_tap_select(`ReadEnable-1:0));
        tap_sel_done        <= data_tap_inc_done;
  
  end if;
 end if;
end process;

--****************************************************************************************************
--  tap_ctrl instances for  DDR_DQS strobes
--****************************************************************************************************


tap_ctrl_0: mem_interface_top_tap_ctrl port map
            ( CLK                                               => CAL_CLK,
              RESET                     => RESET_CAL_CLK,
              RDY_STATUS                => idelay_ctrl_rdy ,
              DQS                       => dqs_delayed(3),
              CTRL_DUMMYREAD_START      => CTRL_DUMMYREAD_START,
              DLYINC                                    => dqs_idelay_inc(0),
              DLYCE                     => dqs_idelay_ce(0),
              DLYRST                    => dqs_idelay_rst(0),
              SEL_DONE                                  => dqs_tap_sel_done(0),
              VALID_DATA_TAP_COUNT      => valid_tap_count(0),
              DATA_TAP_COUNT             => data_tap_count0(5 downto 0)
           );


--****************************************************************************************************
--  instances of data_tap_inc for each dqs and associated tap_ctrl
--****************************************************************************************************


data_tap_inc_0: mem_interface_top_data_tap_inc port map
             (       
                CLK                                             => CAL_CLK,
                RESET                                   => RESET_CAL_CLK,
                DATA_DLYINC                             => data_idelay_inc(0),
                DATA_DLYCE                      => data_idelay_ce(0),
                DATA_DLYRST                             => data_idelay_rst(0),
                DATA_TAP_SEL_DONE               => data_tap_select(0),
                DQS_sel_done                    => dqs_tap_sel_done(0),
                VALID_DATA_TAP_COUNT    => valid_tap_count(0),
                DATA_TAP_COUNT                  => data_tap_count0(5 downto 0)
             ); 


end arch;

---

Author: M.Niegl

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