bcm_signal_delay_vec.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/div/bcm_signal_delay_vec.vhd,v $
--*  $Revision: 1.3.2.4 $                                         *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:45 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;
library work;
use work.main_components.all;

library unisim;

use unisim.vcomponents.all;


entity bcm_signal_delay_vec is
  port (
    CLK           : in  std_logic;
    SCLR          : in  std_logic;
    delay_setting : in  std_logic_vector(7 downto 0);
    data_input    : in  std_logic_vector(31 downto 0);
    data_output   : out std_logic_vector(31 downto 0)
    );
end bcm_signal_delay_vec;


architecture bcm_signal_delay_vec_arc of bcm_signal_delay_vec is

  signal we, rde            : std_logic                     := '0';
  signal addra, addrb, diff : std_logic_vector(7 downto 0)  := (others => '0');


  component shift_reg
    port (
      addra : in  std_logic_vector(7 downto 0);
      addrb : in  std_logic_vector(7 downto 0);
      clka  : in  std_logic;
      clkb  : in  std_logic;
      dina  : in  std_logic_vector(31 downto 0);
      doutb : out std_logic_vector(31 downto 0);
      ena   : in  std_logic;
      enb   : in  std_logic;
      wea   : in  std_logic);
  end component;

begin

  we  <= not SCLR;
  rde <= not SCLR;



  wr_addr : process (CLK, SCLR)
  begin  -- process wr_addr
    if SCLR = '1' then                  -- asynchronous reset (active high)
      addra <= (others => '0');
    elsif CLK'event and CLK = '1' then  -- rising clock edge
      addra <= addra + 1;
    end if;
  end process wr_addr;

  diff <= "00000001" when delay_setting = "00000000" else
          "11111110" when delay_setting = "11111111" else
          delay_setting;

  -- purpose: generate cyclic read address with offset
  -- type   : sequential
  rd_addr : process (CLK, SCLR)
  begin  -- process rd_addr
    if SCLR = '1' then                  -- asynchronous reset (active high)
      addrb <= (others => '0');
    elsif CLK'event and CLK = '1' then  -- rising clock edge
      addrb <= addra - diff;
    end if;
  end process rd_addr;

  bram_shift_reg : shift_reg
    port map (
      addra => addra,
      addrb => addrb,
      clka  => CLK ,
      clkb  => CLK ,
      dina  => data_input,
      doutb => data_output,
      ena   => '1' ,
      enb   => rde ,
      wea   => we 
      );

end bcm_signal_delay_vec_arc;

---

Author: M.Niegl

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