ddr_chksum_cal.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/eth/ddr_chksum_cal.vhd,v $
--*  $Revision: 2.4.2.4 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:46 $                              *



--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

library unisim;

use unisim.vcomponents.all;




entity ddr_chksum_cal is
  
  port (
    CLK        : in  std_logic;
    RESET      : in  std_logic;
    EN         : in  std_logic;
    DATA_IN    : in  std_logic_vector(63 downto 0);
    WRITE_DONE : in  std_logic;
    READ_DATA  : in  std_logic;
    CAL_COMPL  : out std_logic;
    DATA_OUT   : out std_logic_vector(15 downto 0)
    );

end ddr_chksum_cal;




architecture ddr_dsp_chksum_cal_arc of ddr_chksum_cal is

  signal accu_res, done_i, wrd_sy : std_logic                     := '0';
  signal wrd_sy_msk               : std_logic                     := '0';
  signal accu_out1, accu_out2     : std_logic_vector(47 downto 0) := (others => '0');
  signal accu_cout1, accu_cout2   : std_logic_vector(47 downto 0) := (others => '0');
  signal out32, cout32            : std_logic_vector(47 downto 0) := (others => '0');
  signal out16, cout16            : std_logic_vector(47 downto 0) := (others => '0');
  signal last_val                 : std_logic_vector(15 downto 0) := (others => '0');


  component ddr_chksum_accu
    port (
      AB_IN      : in  std_logic_vector (31 downto 0);
      CEA_IN     : in  std_logic;
      CEB_IN     : in  std_logic;
      CECTRL_IN  : in  std_logic;
      CEM_IN     : in  std_logic;
      CEP_IN     : in  std_logic;
      CLK_IN     : in  std_logic;
      LOAD_IN    : in  std_logic;
      RSTA_IN    : in  std_logic;
      RSTB_IN    : in  std_logic;
      RSTCTRL_IN : in  std_logic;
      RSTM_IN    : in  std_logic;
      RSTP_IN    : in  std_logic;
      BCOUT_OUT  : out std_logic_vector (17 downto 0);
      PCOUT_OUT  : out std_logic_vector (47 downto 0);
      P_OUT      : out std_logic_vector (47 downto 0));
  end component;


  component ddr_chksum_adder
    port (
      AB_IN         : in  std_logic_vector (31 downto 0);
      CARRYIN_IN    : in  std_logic;
      CEA_IN        : in  std_logic;
      CEB_IN        : in  std_logic;
      CECINSUB_IN   : in  std_logic;
      CEC_IN        : in  std_logic;
      CEM_IN        : in  std_logic;
      CEP_IN        : in  std_logic;
      CLK_IN        : in  std_logic;
      C_IN          : in  std_logic_vector (31 downto 0);
      RSTA_IN       : in  std_logic;
      RSTB_IN       : in  std_logic;
      RSTCARRYIN_IN : in  std_logic;
      RSTC_IN       : in  std_logic;
      RSTM_IN       : in  std_logic;
      RSTP_IN       : in  std_logic;
      BCOUT_OUT     : out std_logic_vector (17 downto 0);
      PCOUT_OUT     : out std_logic_vector (47 downto 0);
      P_OUT         : out std_logic_vector (47 downto 0));
  end component;


  component edge is
    port (
      CLK   : in  std_logic;
      A     : in  std_logic;
      PULSE : out std_logic);
  end component edge;

begin  -- ddr_dsp_chksum_cal_arc

  accu_res <= RESET or wrd_sy;


  sync_wr_done : entity work.edge     port map
    (
      CLK   => CLK ,
      A     => WRITE_DONE,
      PULSE => wrd_sy
      );

  wrd_sy_msk <= wrd_sy and (not RESET);


  done_del : SRL16
    generic map (
      INIT => X"0000")
    port map (
      Q   => done_i ,                    -- SRL data output
      A0  => '0' ,                       -- Select[0] input
      A1  => '0' ,                       -- Select[1] input
      A2  => '0' ,                       -- Select[2] input
      A3  => '1' ,                       -- Select[3] input
      CLK => CLK ,                       -- Clock input
      D   => wrd_sy_msk                 -- SRL data input
      );


  ddr_chksum_accu_1 : ddr_chksum_accu
    port map
    (
      AB_IN      => DATA_IN(31 downto 0),
      CEA_IN     => EN,
      CEB_IN     => EN,
      CECTRL_IN  => EN,
      CEM_IN     => EN,
      CEP_IN     => EN,
      CLK_IN     => CLK,
      LOAD_IN    => EN,
      RSTA_IN    => accu_res,
      RSTB_IN    => accu_res,
      RSTCTRL_IN => accu_res,
      RSTM_IN    => accu_res,
      RSTP_IN    => accu_res,
      BCOUT_OUT  => open,
      PCOUT_OUT  => open,
      P_OUT      => accu_out1
      );


  ddr_chksum_accu_2 : ddr_chksum_accu
    port map
    (
      AB_IN      => DATA_IN(63 downto 32),
      CEA_IN     => EN,
      CEB_IN     => EN,
      CECTRL_IN  => EN,
      CEM_IN     => EN,
      CEP_IN     => EN,
      CLK_IN     => CLK,
      LOAD_IN    => EN,
      RSTA_IN    => accu_res,
      RSTB_IN    => accu_res,
      RSTCTRL_IN => accu_res,
      RSTM_IN    => accu_res ,
      RSTP_IN    => accu_res,
      BCOUT_OUT  => open,
      PCOUT_OUT  => open,
      P_OUT      => accu_out2
      );


  ddr_chksum_add_in_1 : entity work.ddr_chksum_adder     port map
    (
      AB_IN              => accu_out1(31 downto 0),
      CARRYIN_IN         => '0',
      CEA_IN             => EN,
      CEB_IN             => EN,
      CECINSUB_IN        => EN,
      CEC_IN             => EN,
      CEM_IN             => EN,
      CEP_IN             => EN,
      CLK_IN             => CLK,
      C_IN(31 downto 16) => x"0000",
      C_IN(15 downto 0)  => accu_out1(47 downto 32),
      RSTA_IN             => RESET,
      RSTB_IN            => RESET,
      RSTCARRYIN_IN      => RESET,
      RSTC_IN            => RESET,
      RSTM_IN            => RESET,
      RSTP_IN            => RESET,
      BCOUT_OUT          => open,
      PCOUT_OUT          => open,
      P_OUT              => accu_cout1
      );


  ddr_chksum_add_in_2 : entity work.ddr_chksum_adder     port map
    (
      AB_IN              => accu_out2(31 downto 0),
      CARRYIN_IN         => '0',
      CEA_IN             => EN,
      CEB_IN             => EN,
      CECINSUB_IN        => EN,
      CEC_IN             => EN,
      CEM_IN             => EN,
      CEP_IN             => EN,
      CLK_IN             => CLK,
      C_IN(31 downto 16) => x"0000",
      C_IN(15 downto 0)  => accu_out2(47 downto 32),
      RSTA_IN            => RESET,
      RSTB_IN            => RESET,
      RSTCARRYIN_IN      => RESET,
      RSTC_IN            => RESET,
      RSTM_IN            => RESET,
      RSTP_IN            => RESET,
      BCOUT_OUT          => open,
      PCOUT_OUT          => open,
      P_OUT              => accu_cout2
      );


  ddr_chksum_combine_1 : entity work.ddr_chksum_adder     port map
    (
      AB_IN         => accu_cout1(31 downto 0),
      CARRYIN_IN    => '0',
      CEA_IN        => EN,
      CEB_IN        => EN,
      CECINSUB_IN   => EN,
      CEC_IN        => EN,
      CEM_IN        => EN,
      CEP_IN        => EN,
      CLK_IN        => CLK,
      C_IN          => accu_cout2(31 downto 0),
      RSTA_IN       => RESET,
      RSTB_IN       => RESET,
      RSTCARRYIN_IN => RESET,
      RSTC_IN       => RESET,
      RSTM_IN       => RESET,
      RSTP_IN       => RESET,
      BCOUT_OUT     => open,
      PCOUT_OUT     => open,
      P_OUT         => out32
      );


  ddr_chksum_add_in_3 : entity work.ddr_chksum_adder     port map
    (
      AB_IN              => out32(31 downto 0),
      CARRYIN_IN         => '0',
      CEA_IN             => EN,
      CEB_IN             => EN,
      CECINSUB_IN        => EN,
      CEC_IN             => EN,
      CEM_IN             => EN,
      CEP_IN             => EN,
      CLK_IN              => CLK,
      C_IN(31 downto 16) => x"0000",
      C_IN(15 downto 0)  => out32(47 downto 32),
      RSTA_IN            => RESET,
      RSTB_IN            => RESET,
      RSTCARRYIN_IN      => RESET,
      RSTC_IN            => RESET,
      RSTM_IN            => RESET,
      RSTP_IN            => RESET,
      BCOUT_OUT          => open,
      PCOUT_OUT          => open,
      P_OUT              => cout32
      );


  ddr_chksum_combine_2 : entity work.ddr_chksum_adder     port map
    (
      AB_IN(31 downto 16) => x"0000",
      AB_IN(15 downto 0)  => cout32(15 downto 0),
      CARRYIN_IN          => '0',
      CEA_IN              => EN,
      CEB_IN              => EN,
      CECINSUB_IN         => EN,
      CEC_IN              => EN,
      CEM_IN              => EN,
      CEP_IN              => EN,
      CLK_IN              => CLK,
      C_IN(31 downto 16)  => x"0000",
      C_IN(15 downto 0)   => cout32(31 downto 16),
      RSTA_IN             => RESET,
      RSTB_IN             => RESET,
      RSTCARRYIN_IN       => RESET,
      RSTC_IN             => RESET,
      RSTM_IN             => RESET,
      RSTP_IN             => RESET,
      BCOUT_OUT           => open,
      PCOUT_OUT           => open,
      P_OUT               => out16
      );


  ddr_chksum_add_in_4 : entity work.ddr_chksum_adder     port map
    (
      AB_IN(31 downto 16) => x"0000",
      AB_IN(15 downto 0)  => out16(15 downto 0),
      CARRYIN_IN          => '0',
      CEA_IN              => EN,
      CEB_IN              => EN,
      CECINSUB_IN         => EN,
      CEC_IN              => EN,
      CEM_IN              => EN,
      CEP_IN              => EN,
      CLK_IN              => CLK,
      C_IN(31 downto 16)  => x"0000",
      C_IN(15 downto 0)   => out16(31 downto 16),
      RSTA_IN             => RESET,
      RSTB_IN             => RESET,
      RSTCARRYIN_IN       => RESET,
      RSTC_IN             => RESET,
      RSTM_IN             => RESET,
      RSTP_IN             => RESET,
      BCOUT_OUT           => open,
      PCOUT_OUT           => open,
      P_OUT               => cout16
      );

  -- latch last computed value
  last_val <= cout16(15 downto 0) when done_i = '1' else
              (others => '0') when RESET = '1' else
              last_val;
  DATA_OUT  <= last_val;
  CAL_COMPL <= done_i when rising_edge(CLK);

end ddr_dsp_chksum_cal_arc;

---

Author: M.Niegl

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