BID_cnt.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/div/BID_cnt.vhd,v $
--*  $Revision: 1.6.2.3 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:45 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

library unisim;

use unisim.vcomponents.all;





entity BID_cnt is
  port (
    BC    : in  std_logic;
    BCR   : in  std_logic;
    RESET : in  std_logic;
    BID   : out std_logic_vector (11 downto 0));


  attribute use_dsp48            : string;

  attribute use_dsp48 of BID_cnt : entity is "yes";

end BID_cnt;





architecture BID_cnt_arc of BID_cnt is

----------------------------- signals ------------------------------------
  signal bid_i   : std_logic_vector (11 downto 0) := (others => '0');
  signal bcr_i   : std_logic                      := '0';
  signal bcr2_i  : std_logic                      := '0';
  signal reset_i : std_logic                      := '0';

begin

  BID <= bid_i;


  BID_reset : process(BC)
  begin
    if BC'event and BC = '1' then
      bcr_i  <= BCR;
      bcr2_i <= bcr_i;
    end if;
  end process BID_reset;

  reset_i <= (bcr_i and (not(bcr2_i))) or RESET;


  BID_cnt : process(BC)
  begin
    if BC'event and BC = '1' then
      if reset_i = '1' then
        bid_i <= (others => '0');
      else
        bid_i <= bid_i + 1;
      end if;
    end if;
  end process BID_cnt;

end BID_cnt_arc;

---

Author: M.Niegl

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