addsub48.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/coin/addsub48.vhd,v $
--*  $Revision: 1.4.2.3 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:42 $                              *


--*                                                            *
--**************************************************************
-------------------------------------------------------------------------------- 
-- Copyright (c) 2004 Xilinx, Inc. 
-- All Rights Reserved 
-------------------------------------------------------------------------------- 
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /   Vendor: Xilinx 
-- \   \   \/    Author: Latha Pillai, Advanced Product Group, Xilinx, Inc.
--  \   \        Filename: ADDSUB48
--  /   /        Date Last Modified:  November 8, 2004 
-- /___/   /\    Date Created: June 23, 2004 
-- \   \  /  \ 
--  \___\/\___\ 
-------------------------------------------------------------------------------- 
--------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

library unisim;

use unisim.vcomponents.all;










entity ADDSUB48 is
  port (
    CLK    : in  std_logic;
    RST    : in  std_logic;
    C_IN   : in  std_logic_vector(6 downto 0);
    PC_IN  : in  std_logic_vector(6 downto 0);
    RESULT : out std_logic_vector(6 downto 0)
    );   
end entity ADDSUB48;








architecture ADDSUB48_ARCH of ADDSUB48 is
-----------------------------------------------------------------
-----------------------------------------------------------------

--Signal Declarations:
  signal LOW_18bit      : std_logic_vector(17 downto 0);
  signal LOW_48bit      : std_logic_vector(47 downto 0);
  signal LOW_1bit       : std_logic;
  signal HIGH_1bit      : std_logic;
  signal CARRYINSEL_bit : std_logic_vector(1 downto 0);
  signal c_i            : std_logic_vector(17 downto 0);
  signal pc_i           : std_logic_vector(47 downto 0);

  signal OPMODE_bit : std_logic_vector(6 downto 0);
  signal ADD_SUB    : std_logic;
  signal ADDSUB_OUT : std_logic_vector(47 downto 0);
  signal res_i      : std_logic_vector(6 downto 0) := (others => '0');
  signal rout       : std_logic_vector(6 downto 0) := (others => '0');


------------------------------------------------------------------
-- Architecture Section: instantiation block 1

begin

-- static assignments
  LOW_18bit      <= "000000000000000000";
  LOW_48bit      <= "000000000000000000000000000000000000000000000000";
  LOW_1bit       <= '0';
  HIGH_1bit      <= '1';
  CARRYINSEL_bit <= "00";
  OPMODE_bit     <= "0110011";
  ADD_SUB        <= '1';                -- 0 = add, 1 = sub

-- output assignments
  RESULT <= rout;

-- input assignments
  c_i  <= LOW_48bit(17 downto 7) & C_IN;
  pc_i <= LOW_48bit(47 downto 7) & PC_IN;



  DSP48_1 : DSP48 generic map (
    AREG          => 0,  -- Number of pipeline registers on the A input, 0, 1 or 2
    BREG          => 0,  -- Number of pipeline registers on the B input, 0, 1 or 2
    B_INPUT       => "DIRECT",          -- B input DIRECT from fabric 
    --or CASCADE from another DSP48
    CARRYINREG    => 0,                 -- Number of pipeline registers 
    -- for the CARRYIN input, 0 or 1
    CARRYINSELREG => 0,                 -- Number of pipeline registers 
    -- for the CARRYINSEL, 0 or 1
    CREG          => 0,  -- Number of pipeline registers on the C input, 0 or 1
    LEGACY_MODE   => "MULT18X18S",      -- Backward compatibility, NONE, 
    -- MULT18X18 or MULT18X18S
    MREG          => 1,  -- Number of multiplier pipeline registers, 0 or 1
    OPMODEREG     => 0,  -- Number of pipeline registers on OPMODE input, 0 or 1
    PREG          => 1,  -- Number of pipeline registers on the P output, 0 or 1
    SUBTRACTREG   => 0)                 -- Number of pipeline registers on the 
    -- SUBTRACT input, 0 or 1
    
    port map (
      A           => LOW_18bit,
      B           => c_i,
      C           => pc_i,
      BCIN       => LOW_18bit,
      PCIN       => LOW_48bit,
      OPMODE     => OPMODE_bit ,
      SUBTRACT   => ADD_SUB,
      CARRYIN    => LOW_1bit,
      CARRYINSEL => CARRYINSEL_bit,
      CLK        => CLK,
      CEA        => LOW_1bit,
      CEB        => LOW_1bit,
      CEC        => HIGH_1bit,
      CEP         => HIGH_1bit,
      CEM        => HIGH_1bit,
      CECTRL     => LOW_1bit,
      CECARRYIN  => LOW_1bit,
      CECINSUB   => HIGH_1bit,
      RSTA       => RST,
      RSTB       => RST,
      RSTC       => RST,
      RSTP       => RST,
      RSTM       => RST,
      RSTCTRL    => RST,
      RSTCARRYIN => RST,
      BCOUT      => open,
      P           => ADDSUB_OUT ,
      PCOUT      => open
      );

  res_i <= ADDSUB_OUT(6 downto 0);


  process(res_i)
    variable r_i : std_logic_vector(6 downto 0) := (others => '0');
  begin
    if res_i(6) = '1' then
      for i in 6 downto 0 loop
        r_i(i) := not(res_i(i));
      end loop;
      r_i := r_i + 1;
    else
      r_i := res_i;
    end if;
    rout <= r_i;
  end process;
  
end ADDSUB48_ARCH;

---

Author: M.Niegl

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