bcm_emac_fifo.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/eth/bcm_emac_fifo.vhd,v $
--*  $Revision: 2.1.2.3 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:46 $                              *


--*                                                            *
--**************************************************************
--------------------------------------------------------------------------------
--     This file is owned and controlled by Xilinx and must be used           --
--     solely for design, simulation, implementation and creation of          --
--     design files limited to Xilinx devices or technologies. Use            --
--     with non-Xilinx devices or technologies is expressly prohibited        --
--     and immediately terminates your license.                               --
--                                                                            --
--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
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--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
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--     (c) Copyright 1995-2007 Xilinx, Inc.                                   --
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--------------------------------------------------------------------------------
-- You must compile the wrapper file bcm_emac_fifo.vhd when simulating
-- the core, bcm_emac_fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).


library ieee;

use ieee.std_logic_1164.all;
-- synthesis translate_off
library XilinxCoreLib;
-- synthesis translate_on



entity bcm_emac_fifo is
  port (
    din    : in  std_logic_vector(8 downto 0);
    rd_clk : in  std_logic;
    rd_en  : in  std_logic;
    rst    : in  std_logic;
    wr_clk : in  std_logic;
    wr_en  : in  std_logic;
    dout   : out std_logic_vector(8 downto 0);
    empty  : out std_logic;
    full   : out std_logic
    );
end bcm_emac_fifo;


architecture bcm_emac_fifo_a of bcm_emac_fifo is
-- synthesis translate_off

  component wrapped_bcm_emac_fifo
    port (
      din    : in  std_logic_vector(8 downto 0);
      rd_clk : in  std_logic;
      rd_en  : in  std_logic;
      rst    : in  std_logic;
      wr_clk : in  std_logic;
      wr_en  : in  std_logic;
      dout   : out std_logic_vector(8 downto 0);
      empty  : out std_logic;
      full   : out std_logic);
  end component;

-- Configuration specification 
  for all : wrapped_bcm_emac_fifo use entity XilinxCoreLib.fifo_generator_v3_3(behavioral)
    generic map(
      c_rd_freq                      => 12,
      c_wr_response_latency          => 1,
      c_has_srst                     => 0,
      c_has_rd_data_count            => 0,
      c_din_width                    => 9,
      c_has_wr_data_count            => 0,
      c_implementation_type          => 3,
      c_family                       => "virtex4",
      c_has_wr_rst                   => 0,
      c_wr_freq                      => 100,
      c_underflow_low                => 0,
      c_has_meminit_file             => 0,
      c_has_overflow                 => 0,
      c_preload_latency              => 1,
      c_dout_width                   => 9,
      c_rd_depth                     => 2048,
      c_default_value                => "BlankString",
      c_mif_file_name                => "BlankString",
      c_has_underflow                => 0,
      c_has_rd_rst                   => 0,
      c_has_almost_full              => 0,
      c_has_rst                      => 1,
      c_data_count_width             => 11,
      c_has_wr_ack                   => 0,
      c_use_ecc                      => 0,
      c_wr_ack_low                   => 0,
      c_common_clock                 => 0,
      c_rd_pntr_width                => 11,
      c_has_almost_empty             => 0,
      c_rd_data_count_width          => 11,
      c_enable_rlocs                 => 0,
      c_wr_pntr_width                => 11,
      c_overflow_low                 => 0,
      c_prog_empty_type              => 0,
      c_optimization_mode            => 0,
      c_wr_data_count_width          => 11,
      c_preload_regs                 => 0,
      c_dout_rst_val                 => "0",
      c_has_data_count               => 0,
      c_prog_full_thresh_negate_val  => 2059,
      c_wr_depth                     => 2048,
      c_prog_empty_thresh_negate_val => 22,
      c_prog_empty_thresh_assert_val => 21,
      c_has_valid                    => 0,
      c_init_wr_pntr_val             => 0,
      c_prog_full_thresh_assert_val  => 2060,
      c_use_fifo16_flags             => 0,
      c_has_backup                   => 0,
      c_valid_low                    => 0,
      c_prim_fifo_type               => "2kx9",
      c_count_type                   => 0,
      c_prog_full_type               => 0,
      c_memory_type                  => 4);
-- synthesis translate_on
begin
-- synthesis translate_off
  U0 : wrapped_bcm_emac_fifo
    port map (
      din    => din ,
      rd_clk => rd_clk,
      rd_en  => rd_en,
      rst    => rst ,
      wr_clk => wr_clk,
      wr_en  => wr_en,
      dout   => dout,
      empty  => empty,
      full   => full);
-- synthesis translate_on

end bcm_emac_fifo_a;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:02 2008 for BCM-AAA by  1.5.7.1-20081012