status_collector.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/div/status_collector.vhd,v $
--*  $Revision: 1.16.2.3 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:45 $                              *


--*                                                            *
--**************************************************************


library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

library work;

use work.build_parameters.all;







entity status_collector is
  
  port (
    DEBUG           : out std_logic_vector(14 downto 0);
    EMAC_CLK        : in  std_logic;
    RATES_CLK       : in  std_logic;
    STATUS_CLK      : in  std_logic;
    RIO_CLK         : in  std_logic;
    RESET           : in  std_logic;
    START           : in  std_logic;
    FETCH_BYTE      : in  std_logic;
    FETCH_CHKSUM    : in  std_logic;
    ERROR_FLAG      : in  std_logic;
    EXT_CLK_DET     : in  std_logic;
    RIO_DAQ         : in  std_logic;
    RIO_SATA        : in  std_logic;
    MODE            : in  std_logic;
    DCM_STATUS      : in  std_logic;
    ROD_STATUS      : in  std_logic;
    FPGA_ID         : in  std_logic_vector(7 downto 0)   := x"00";
    MAIN_FSM        : in  std_logic_vector(7 downto 0);
    ERROR_CODE      : in  std_logic_vector(31 downto 0);
    DSS_CIBU_STATUS : in  std_logic_vector(31 downto 0);
    INPUT_STATUS    : in  std_logic_vector(63 downto 0);
    TDAQ_PARAMS     : in  std_logic_vector(159 downto 0) := (others => '0');
    HITRATE_CH1     : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_CH2     : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_CH3     : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_CH4     : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_CH5     : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_CH6     : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_CH7     : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_CH8     : in  std_logic_vector(31 downto 0)  := (others => '0');
    ALGO_STATE      : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_A_CH1   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_A_CH2   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_A_CH3   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_A_CH4   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_A_CH5   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_A_CH6   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_A_CH7   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_A_CH8   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_B_CH1   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_B_CH2   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_B_CH3   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_B_CH4   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_B_CH5   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_B_CH6   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_B_CH7   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_B_CH8   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_C_CH1   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_C_CH2   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_C_CH3   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_C_CH4   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_C_CH5   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_C_CH6   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_C_CH7   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_C_CH8   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_D_CH1   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_D_CH2   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_D_CH3   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_D_CH4   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_D_CH5   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_D_CH6   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_D_CH7   : in  std_logic_vector(31 downto 0)  := (others => '0');
    HITRATE_D_CH8   : in  std_logic_vector(31 downto 0)  := (others => '0');
    ASM_DONE        : out std_logic;
    TRANS_DONE      : out std_logic;
    CHKSUM_OUT      : out std_logic_vector(15 downto 0);
    DATA_OUT        : out std_logic_vector(7 downto 0)
    );

  attribute MAX_FANOUT                     : string;
  attribute MAX_FANOUT of status_collector : entity is "10";
  
end status_collector;






architecture status_collector_arc of status_collector is


  component edge
    port(
      CLK   : in  std_logic;
      A     : in  std_logic;
      PULSE : out std_logic
      );
  end component;


  component ddr2_chksum_cal
    port(
      CLK        : in  std_logic;
      RESET      : in  std_logic;
      EN         : in  std_logic;
      DATA_IN    : in  std_logic_vector(127 downto 0);
      WRITE_DONE : in  std_logic;
      READ_DATA  : in  std_logic;
      CAL_COMPL  : out std_logic;
      DATA_OUT   : out std_logic_vector(15 downto 0)
      );
  end component;


  constant hr_vld       : std_logic_vector(7 downto 0) := kSendHitRate;

  constant hr_vld_bit   : std_logic                    := hr_vld(7) and hr_vld(6) and hr_vld(5) and hr_vld(4) and hr_vld(3) and hr_vld(2) and hr_vld(1) and hr_vld(0);

  constant algo_vld     : std_logic_vector(7 downto 0) := kSendAlgoRate;

  constant algo_vld_bit : std_logic                    := algo_vld(7) and algo_vld(6) and algo_vld(5) and algo_vld(4) and algo_vld(3) and algo_vld(2) and algo_vld(1) and algo_vld(0);

  constant reserved     : std_logic_vector(7 downto 0) := x"00";

  alias rsv is reserved;

  signal en_wr        : std_logic                      := '0';
  signal en_asm       : std_logic                      := '0';
  signal en_cal       : std_logic                      := '0';
  signal en_calfsm    : std_logic                      := '0';
  signal done_i       : std_logic                      := '0';
  signal cal_wr_done  : std_logic                      := '0';
  signal cal_done     : std_logic                      := '0';
  signal start_p_i    : std_logic                      := '0';
  signal start_p_ii   : std_logic                      := '0';
  signal start_del    : std_logic                      := '0';
  signal chksum_out_i : std_logic_vector(15 downto 0)  := (others => '0');
  signal chk_in       : std_logic_vector(127 downto 0) := (others => '0');
  signal reg_fpga_id  : std_logic_vector(7 downto 0)   := (others => '0');
  signal pktcnt       : std_logic_vector(7 downto 0)   := (others => '0');
  signal pktcntwr     : std_logic_vector(7 downto 0)   := (others => '0');
  signal reg_dsscibu  : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_err      : std_logic_vector(7 downto 0)   := (others => '0');
  signal reg_extclk   : std_logic_vector(7 downto 0)   := (others => '0');
  signal reg_daq      : std_logic_vector(7 downto 0)   := (others => '0');
  signal reg_sata     : std_logic_vector(7 downto 0)   := (others => '0');
  signal reg_mac      : std_logic_vector(7 downto 0)   := (others => '0');
  signal reg_dcm      : std_logic_vector(7 downto 0)   := (others => '0');
  signal reg_rod      : std_logic_vector(7 downto 0)   := (others => '0');
  signal reg_fsm      : std_logic_vector(7 downto 0)   := (others => '0');
  signal reg_ins      : std_logic_vector(63 downto 0)  := (others => '0');
  signal reg_tdaq     : std_logic_vector(159 downto 0) := (others => '0');
  signal reg_errcode  : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_algo     : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_1     : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_2     : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_3     : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_4     : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_5     : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_6     : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_7     : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_8     : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_a1    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_a2    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_a3    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_a4    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_a5    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_a6    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_a7    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_a8    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_b1    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_b2    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_b3    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_b4    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_b5    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_b6    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_b7    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_b8    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_c1    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_c2    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_c3    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_c4    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_c5    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_c6    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_c7    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_c8    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_d1    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_d2    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_d3    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_d4    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_d5    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_d6    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_d7    : std_logic_vector(31 downto 0)  := (others => '0');
  signal reg_hr_d8    : std_logic_vector(31 downto 0)  := (others => '0');
  signal data_out_i   : std_logic_vector(7 downto 0)   := (others => '0');
  signal ocnt         : integer range 0 to 255         := 0;
  signal ocnto        : integer                        := 255;
  signal cnt          : integer range 0 to 31          := 0;
  signal cnto         : integer                        := 31;

begin  -- status_collector_arc

  DEBUG(14 downto 10) <= conv_std_logic_vector(cnt, 5);
  DEBUG(9)            <= start_p_i;
  DEBUG(8)            <= start_del;
  DEBUG(7)            <= done_i;
  DEBUG(6)            <= cal_done;
  DEBUG(5)            <= en_asm;
  DEBUG(4)            <= en_calfsm;
  DEBUG(3)            <= cal_wr_done;
  DEBUG(2)            <= en_wr;
  DEBUG(1)            <= en_cal;
  DEBUG(0)            <= '0';


  start_pulse : edge
    port map(
      CLK   => EMAC_CLK ,
      A     => START ,
      PULSE => start_p_i 
      );

  start_p_ii <= start_p_i when rising_edge(EMAC_CLK);
  start_del  <= START     when rising_edge(EMAC_CLK);
  TRANS_DONE <= done_i;
  ASM_DONE   <= cal_done;


  latch_enable_assembly : process (EMAC_CLK, RESET)
  begin  -- process latch_enable_assembly
    if RESET = '1' then                 -- asynchronous reset (active high)
      en_asm <= '0';
    elsif EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
      if done_i = '1' then
        en_asm <= '0';
      elsif start_p_ii = '1' then
        en_asm <= '1';
      end if;
    end if;
  end process latch_enable_assembly;


  latch_enable_calculation : process (EMAC_CLK, RESET)
  begin  -- process latch_enable_assembly
    if RESET = '1' then                 -- asynchronous reset (active high)
      en_calfsm <= '0';
    elsif EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
      if cal_wr_done = '1' then
        en_calfsm <= '0';
      elsif start_p_i = '1' then
        en_calfsm <= '1';
      end if;
    end if;
  end process latch_enable_calculation;

  en_wr <= not en_asm;


  pkt_id_cnt : process (EMAC_CLK, RESET)
  begin  -- process pkt_id_cnt
    if RESET = '1' then                 -- asynchronous reset (active high)
      pktcnt   <= (others => '0');
      pktcntwr <= (others => '0');
    elsif EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
      if start_p_i = '1' then
        pktcntwr <= pktcnt;
        pktcnt   <= pktcnt + 1;
      end if;
    end if;
  end process pkt_id_cnt;


  rate_registers : process (RATES_CLK, RESET)
  begin  -- process registers
    if RESET = '1' then                 -- asynchronous reset (active high)
      reg_dsscibu <= (others => '0');
      reg_rod     <= (others => '0');
      reg_tdaq    <= (others => '0');
      reg_algo    <= (others => '0');
      reg_hr_1    <= (others => '0');
      reg_hr_2    <= (others => '0');
      reg_hr_3    <= (others => '0');
      reg_hr_4    <= (others => '0');
      reg_hr_5    <= (others => '0');
      reg_hr_6    <= (others => '0');
      reg_hr_7    <= (others => '0');
      reg_hr_8    <= (others => '0');
      reg_hr_a1   <= (others => '0');
      reg_hr_a2   <= (others => '0');
      reg_hr_a3   <= (others => '0');
      reg_hr_a4   <= (others => '0');
      reg_hr_a5   <= (others => '0');
      reg_hr_a6   <= (others => '0');
      reg_hr_a7   <= (others => '0');
      reg_hr_a8   <= (others => '0');
      reg_hr_b1   <= (others => '0');
      reg_hr_b2   <= (others => '0');
      reg_hr_b3   <= (others => '0');
      reg_hr_b4   <= (others => '0');
      reg_hr_b5   <= (others => '0');
      reg_hr_b6   <= (others => '0');
      reg_hr_b7   <= (others => '0');
      reg_hr_b8   <= (others => '0');
      reg_hr_c1   <= (others => '0');
      reg_hr_c2   <= (others => '0');
      reg_hr_c3   <= (others => '0');
      reg_hr_c4   <= (others => '0');
      reg_hr_c5   <= (others => '0');
      reg_hr_c6   <= (others => '0');
      reg_hr_c7   <= (others => '0');
      reg_hr_c8   <= (others => '0');
      reg_hr_d1   <= (others => '0');
      reg_hr_d2   <= (others => '0');
      reg_hr_d3   <= (others => '0');
      reg_hr_d4   <= (others => '0');
      reg_hr_d5   <= (others => '0');
      reg_hr_d6   <= (others => '0');
      reg_hr_d7   <= (others => '0');
      reg_hr_d8   <= (others => '0');
    elsif RATES_CLK'event and RATES_CLK = '1' then  -- rising clock edge
      if en_wr = '1' then
        if ROD_STATUS = '1' then
          reg_rod <= (others => '1');
        else
          reg_rod <= (others => '0');
        end if;
        reg_tdaq    <= TDAQ_PARAMS;
        reg_dsscibu <= DSS_CIBU_STATUS;
        reg_algo    <= ALGO_STATE;
        if hr_vld_bit = '1' then
          reg_hr_1 <= HITRATE_CH1;
          reg_hr_2 <= HITRATE_CH2;
          reg_hr_3 <= HITRATE_CH3;
          reg_hr_4 <= HITRATE_CH4;
          reg_hr_5 <= HITRATE_CH5;
          reg_hr_6 <= HITRATE_CH6;
          reg_hr_7 <= HITRATE_CH7;
          reg_hr_8 <= HITRATE_CH8;
        else
          reg_hr_1 <= (others => '0');
          reg_hr_2 <= (others => '0');
          reg_hr_3 <= (others => '0');
          reg_hr_4 <= (others => '0');
          reg_hr_5 <= (others => '0');
          reg_hr_6 <= (others => '0');
          reg_hr_7 <= (others => '0');
          reg_hr_8 <= (others => '0');
        end if;
        if algo_vld_bit = '1' then
          reg_hr_a1 <= HITRATE_A_CH1;
          reg_hr_a2 <= HITRATE_A_CH2;
          reg_hr_a3 <= HITRATE_A_CH3;
          reg_hr_a4 <= HITRATE_A_CH4;
          reg_hr_a5 <= HITRATE_A_CH5;
          reg_hr_a6 <= HITRATE_A_CH6;
          reg_hr_a7 <= HITRATE_A_CH7;
          reg_hr_a8 <= HITRATE_A_CH8;
          reg_hr_b1 <= HITRATE_B_CH1;
          reg_hr_b2 <= HITRATE_B_CH2;
          reg_hr_b3 <= HITRATE_B_CH3;
          reg_hr_b4 <= HITRATE_B_CH4;
          reg_hr_b5 <= HITRATE_B_CH5;
          reg_hr_b6 <= HITRATE_B_CH6;
          reg_hr_b7 <= HITRATE_B_CH7;
          reg_hr_b8 <= HITRATE_B_CH8;
          reg_hr_c1 <= HITRATE_C_CH1;
          reg_hr_c2 <= HITRATE_C_CH2;
          reg_hr_c3 <= HITRATE_C_CH3;
          reg_hr_c4 <= HITRATE_C_CH4;
          reg_hr_c5 <= HITRATE_C_CH5;
          reg_hr_c6 <= HITRATE_C_CH6;
          reg_hr_c7 <= HITRATE_C_CH7;
          reg_hr_c8 <= HITRATE_C_CH8;
          reg_hr_d1 <= HITRATE_D_CH1;
          reg_hr_d2 <= HITRATE_D_CH2;
          reg_hr_d3 <= HITRATE_D_CH3;
          reg_hr_d4 <= HITRATE_D_CH4;
          reg_hr_d5 <= HITRATE_D_CH5;
          reg_hr_d6 <= HITRATE_D_CH6;
          reg_hr_d7 <= HITRATE_D_CH7;
          reg_hr_d8 <= HITRATE_D_CH8;
        else
          reg_hr_a1 <= (others => '0');
          reg_hr_a2 <= (others => '0');
          reg_hr_a3 <= (others => '0');
          reg_hr_a4 <= (others => '0');
          reg_hr_a5 <= (others => '0');
          reg_hr_a6 <= (others => '0');
          reg_hr_a7 <= (others => '0');
          reg_hr_a8 <= (others => '0');
          reg_hr_b1 <= (others => '0');
          reg_hr_b2 <= (others => '0');
          reg_hr_b3 <= (others => '0');
          reg_hr_b4 <= (others => '0');
          reg_hr_b5 <= (others => '0');
          reg_hr_b6 <= (others => '0');
          reg_hr_b7 <= (others => '0');
          reg_hr_b8 <= (others => '0');
          reg_hr_c1 <= (others => '0');
          reg_hr_c2 <= (others => '0');
          reg_hr_c3 <= (others => '0');
          reg_hr_c4 <= (others => '0');
          reg_hr_c5 <= (others => '0');
          reg_hr_c6 <= (others => '0');
          reg_hr_c7 <= (others => '0');
          reg_hr_c8 <= (others => '0');
          reg_hr_d1 <= (others => '0');
          reg_hr_d2 <= (others => '0');
          reg_hr_d3 <= (others => '0');
          reg_hr_d4 <= (others => '0');
          reg_hr_d5 <= (others => '0');
          reg_hr_d6 <= (others => '0');
          reg_hr_d7 <= (others => '0');
          reg_hr_d8 <= (others => '0');
        end if;
      end if;
    end if;
  end process rate_registers;


  input_status_registers : process (RIO_CLK, RESET)
  begin  -- process input_status_registers
    if RESET = '1' then                 -- asynchronous reset (active high)
      reg_daq  <= (others => '0');
      reg_sata <= (others => '0');
      reg_ins  <= (others => '0');
    elsif RIO_CLK'event and RIO_CLK = '1' then  -- rising clock edge
      if en_wr = '1' then
        reg_ins <= INPUT_STATUS;
        if RIO_DAQ = '1' then
          reg_daq <= (others => '1');
        else
          reg_daq <= (others => '0');
        end if;
        if RIO_SATA = '1' then
          reg_sata <= (others => '1');
        else
          reg_sata <= (others => '0');
        end if;
      end if;
    end if;
  end process input_status_registers;


  status_registers : process (STATUS_CLK, RESET)
  begin  -- process status_registers
    if RESET = '1' then                 -- asynchronous reset (active high)
      reg_err     <= (others => '0');
      reg_errcode <= (others => '0');
      reg_extclk  <= (others => '0');
      reg_dcm     <= (others => '0');
      reg_fsm     <= (others => '0');
    elsif STATUS_CLK'event and STATUS_CLK = '1' then  -- rising clock edge
      if en_wr = '1' then
        if ERROR_FLAG = '1' then
          reg_err <= (others => '1');
        else
          reg_err <= (others => '0');
        end if;
        if EXT_CLK_DET = '1' then
          reg_extclk <= (others => '1');
        else
          reg_extclk <= (others => '0');
        end if;
        if DCM_STATUS = '1' then
          reg_dcm <= (others => '1');
        else
          reg_dcm <= (others => '0');
        end if;
        reg_fsm     <= MAIN_FSM;
        reg_errcode <= ERROR_CODE;
      end if;
    end if;
  end process status_registers;


  general_registers : process (EMAC_CLK, RESET)
  begin  -- process general_registers
    if RESET = '1' then                 -- asynchronous reset (active high)
      reg_mac     <= (others => '0');
      reg_fpga_id <= (others => '0');
    elsif EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
      if en_wr = '1' then
        reg_fpga_id <= FPGA_ID;
        if MODE = '1' then
          reg_mac <= (others => '1');
        else
          reg_mac <= (others => '0');
        end if;
      end if;
    end if;
  end process general_registers;

  chksum_cnt : process (EMAC_CLK, RESET)
  begin  -- process chksum_cnt
    if RESET = '1' then                 -- asynchronous reset (active high)
      cnt <= 0;
    elsif EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
      if en_calfsm = '1' then
        cnt <= cnt + 1;
        if cnt > 15 then
          cnt <= cnt;
        end if;
      else
        cnt <= 0;
      end if;
    end if;
  end process chksum_cnt;

  checksum_assembly : process (cnt)
  begin  -- process checksum_assembly
    cnto        <= cnt - 1;
    en_cal      <= '1';
    cal_wr_done <= '0';
    case cnto is
      when 0 => chk_in <= hr_vld & algo_vld & reg_fpga_id & pktcntwr & reg_err & reg_extclk & reg_fsm & reg_daq &
                          reg_sata & reg_rod & reg_mac & reg_dcm & reg_dsscibu;
      when 1  => chk_in <= reg_errcode & reg_ins & reg_tdaq(159 downto 128);
      when 2  => chk_in <= reg_tdaq(127 downto 0);
      when 3  => chk_in <= reg_hr_1 & reg_hr_2 & reg_hr_3 & reg_hr_4;
      when 4  => chk_in <= reg_hr_5 & reg_hr_6 & reg_hr_7 & reg_hr_8;
      when 5  => chk_in <= reg_hr_a1 & reg_hr_a2 & reg_hr_a3 & reg_hr_a4;
      when 6  => chk_in <= reg_hr_a5 & reg_hr_a6 & reg_hr_a7 & reg_hr_a8;
      when 7  => chk_in <= reg_hr_b1 & reg_hr_b2 & reg_hr_b3 & reg_hr_b4;
      when 8  => chk_in <= reg_hr_b5 & reg_hr_b6 & reg_hr_b7 & reg_hr_b8;
      when 9  => chk_in <= reg_hr_c1 & reg_hr_c2 & reg_hr_c3 & reg_hr_c4;
      when 10 => chk_in <= reg_hr_c5 & reg_hr_c6 & reg_hr_c7 & reg_hr_c8;
      when 11 => chk_in <= reg_hr_d1 & reg_hr_d2 & reg_hr_d3 & reg_hr_d4;
      when 12 => chk_in <= reg_hr_d5 & reg_hr_d6 & reg_hr_d7 & reg_hr_d8;
      when 13 => chk_in <= reg_algo & x"0000_0000_0000_0000_0000_0000";
      when 14 => chk_in <= (others => '0');
                 cal_wr_done <= '1';
      when others =>
        en_cal      <= '0';
        cal_wr_done <= '0';
        chk_in      <= (others => '0');
    end case;
  end process checksum_assembly;


  chksum_cal : ddr2_chksum_cal
    port map(
      CLK         => EMAC_CLK,
      RESET      => RESET,
      EN          => en_cal,
      DATA_IN    => chk_in,
      WRITE_DONE => cal_wr_done,
      CAL_COMPL  => cal_done,
      READ_DATA  => FETCH_CHKSUM,
      DATA_OUT   => chksum_out_i
      );

  CHKSUM_OUT <= (others => '0') when RESET = '1' else chksum_out_i;

  assembly_cnt : process (EMAC_CLK, RESET)
  begin  -- process assembly_cnt
    if RESET = '1' then                 -- asynchronous reset (active high)
      ocnt <= 0;
    elsif EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
      if FETCH_BYTE = '1' then
        ocnt <= ocnt + 1;
        if ocnt > 212 then
          ocnt <= ocnt;
        end if;
      else
        ocnt <= 0;
      end if;
    end if;
  end process assembly_cnt;

  byte_assembly : process (ocnt)
  begin  -- process byte_assembly
    ocnto  <= ocnt - 1;
    done_i <= '0';
    case ocnto is
      when 0   => data_out_i <= hr_vld;
      when 1   => data_out_i <= algo_vld;
      when 2   => data_out_i <= reg_fpga_id;
      when 3   => data_out_i <= pktcntwr;
      when 4   => data_out_i <= reg_err;
      when 5   => data_out_i <= reg_extclk;
      when 6   => data_out_i <= reg_fsm;
      when 7   => data_out_i <= reg_daq;
      when 8   => data_out_i <= reg_sata;
      when 9   => data_out_i <= reg_rod;
      when 10  => data_out_i <= reg_mac;
      when 11  => data_out_i <= reg_dcm;
      when 12  => data_out_i <= reg_dsscibu(31 downto 24);
      when 13  => data_out_i <= reg_dsscibu(23 downto 16);
      when 14  => data_out_i <= reg_dsscibu(15 downto 8);
      when 15  => data_out_i <= reg_dsscibu(7 downto 0);
      when 16  => data_out_i <= reg_errcode(31 downto 24);
      when 17  => data_out_i <= reg_errcode(23 downto 16);
      when 18  => data_out_i <= reg_errcode(15 downto 8);
      when 19  => data_out_i <= reg_errcode(7 downto 0);
      when 20  => data_out_i <= reg_ins(63 downto 56);
      when 21  => data_out_i <= reg_ins(55 downto 48);
      when 22  => data_out_i <= reg_ins(47 downto 40);
      when 23  => data_out_i <= reg_ins(39 downto 32);
      when 24  => data_out_i <= reg_ins(31 downto 24);
      when 25  => data_out_i <= reg_ins(23 downto 16);
      when 26  => data_out_i <= reg_ins(15 downto 8);
      when 27  => data_out_i <= reg_ins(7 downto 0);
      when 28  => data_out_i <= reg_tdaq(159 downto 152);
      when 29  => data_out_i <= reg_tdaq(151 downto 144);
      when 30  => data_out_i <= reg_tdaq(143 downto 136);
      when 31  => data_out_i <= reg_tdaq(135 downto 128);
      when 32  => data_out_i <= reg_tdaq(127 downto 120);
      when 33  => data_out_i <= reg_tdaq(119 downto 112);
      when 34  => data_out_i <= reg_tdaq(111 downto 104);
      when 35  => data_out_i <= reg_tdaq(103 downto 96);
      when 36  => data_out_i <= reg_tdaq(95 downto 88);
      when 37  => data_out_i <= reg_tdaq(87 downto 80);
      when 38  => data_out_i <= reg_tdaq(79 downto 72);
      when 39  => data_out_i <= reg_tdaq(71 downto 64);
      when 40  => data_out_i <= reg_tdaq(63 downto 56);
      when 41  => data_out_i <= reg_tdaq(55 downto 48);
      when 42  => data_out_i <= reg_tdaq(47 downto 40);
      when 43  => data_out_i <= reg_tdaq(39 downto 32);
      when 44  => data_out_i <= reg_tdaq(31 downto 24);
      when 45  => data_out_i <= reg_tdaq(23 downto 16);
      when 46  => data_out_i <= reg_tdaq(15 downto 8);
      when 47  => data_out_i <= reg_tdaq(7 downto 0);
      when 48  => data_out_i <= reg_hr_1(31 downto 24);
      when 49  => data_out_i <= reg_hr_1(23 downto 16);
      when 50  => data_out_i <= reg_hr_1(15 downto 8);
      when 51  => data_out_i <= reg_hr_1(7 downto 0);
      when 52  => data_out_i <= reg_hr_2(31 downto 24);
      when 53  => data_out_i <= reg_hr_2(23 downto 16);
      when 54  => data_out_i <= reg_hr_2(15 downto 8);
      when 55  => data_out_i <= reg_hr_2(7 downto 0);
      when 56  => data_out_i <= reg_hr_3(31 downto 24);
      when 57  => data_out_i <= reg_hr_3(23 downto 16);
      when 58  => data_out_i <= reg_hr_3(15 downto 8);
      when 59  => data_out_i <= reg_hr_3(7 downto 0);
      when 60  => data_out_i <= reg_hr_4(31 downto 24);
      when 61  => data_out_i <= reg_hr_4(23 downto 16);
      when 62  => data_out_i <= reg_hr_4(15 downto 8);
      when 63  => data_out_i <= reg_hr_4(7 downto 0);
      when 64  => data_out_i <= reg_hr_5(31 downto 24);
      when 65  => data_out_i <= reg_hr_5(23 downto 16);
      when 66  => data_out_i <= reg_hr_5(15 downto 8);
      when 67  => data_out_i <= reg_hr_5(7 downto 0);
      when 68  => data_out_i <= reg_hr_6(31 downto 24);
      when 69  => data_out_i <= reg_hr_6(23 downto 16);
      when 70  => data_out_i <= reg_hr_6(15 downto 8);
      when 71  => data_out_i <= reg_hr_6(7 downto 0);
      when 72  => data_out_i <= reg_hr_7(31 downto 24);
      when 73  => data_out_i <= reg_hr_7(23 downto 16);
      when 74  => data_out_i <= reg_hr_7(15 downto 8);
      when 75  => data_out_i <= reg_hr_7(7 downto 0);
      when 76  => data_out_i <= reg_hr_8(31 downto 24);
      when 77  => data_out_i <= reg_hr_8(23 downto 16);
      when 78  => data_out_i <= reg_hr_8(15 downto 8);
      when 79  => data_out_i <= reg_hr_8(7 downto 0);
      when 80  => data_out_i <= reg_hr_a1(31 downto 24);
      when 81  => data_out_i <= reg_hr_a1(23 downto 16);
      when 82  => data_out_i <= reg_hr_a1(15 downto 8);
      when 83  => data_out_i <= reg_hr_a1(7 downto 0);
      when 84  => data_out_i <= reg_hr_a2(31 downto 24);
      when 85  => data_out_i <= reg_hr_a2(23 downto 16);
      when 86  => data_out_i <= reg_hr_a2(15 downto 8);
      when 87  => data_out_i <= reg_hr_a2(7 downto 0);
      when 88  => data_out_i <= reg_hr_a3(31 downto 24);
      when 89  => data_out_i <= reg_hr_a3(23 downto 16);
      when 90  => data_out_i <= reg_hr_a3(15 downto 8);
      when 91  => data_out_i <= reg_hr_a3(7 downto 0);
      when 92  => data_out_i <= reg_hr_a4(31 downto 24);
      when 93  => data_out_i <= reg_hr_a4(23 downto 16);
      when 94  => data_out_i <= reg_hr_a4(15 downto 8);
      when 95  => data_out_i <= reg_hr_a4(7 downto 0);
      when 96  => data_out_i <= reg_hr_a5(31 downto 24);
      when 97  => data_out_i <= reg_hr_a5(23 downto 16);
      when 98  => data_out_i <= reg_hr_a5(15 downto 8);
      when 99  => data_out_i <= reg_hr_a5(7 downto 0);
      when 100 => data_out_i <= reg_hr_a6(31 downto 24);
      when 101 => data_out_i <= reg_hr_a6(23 downto 16);
      when 102 => data_out_i <= reg_hr_a6(15 downto 8);
      when 103 => data_out_i <= reg_hr_a6(7 downto 0);
      when 104 => data_out_i <= reg_hr_a7(31 downto 24);
      when 105 => data_out_i <= reg_hr_a7(23 downto 16);
      when 106 => data_out_i <= reg_hr_a7(15 downto 8);
      when 107 => data_out_i <= reg_hr_a7(7 downto 0);
      when 108 => data_out_i <= reg_hr_a8(31 downto 24);
      when 109 => data_out_i <= reg_hr_a8(23 downto 16);
      when 110 => data_out_i <= reg_hr_a8(15 downto 8);
      when 111 => data_out_i <= reg_hr_a8(7 downto 0);
      when 112 => data_out_i <= reg_hr_b1(31 downto 24);
      when 113 => data_out_i <= reg_hr_b1(23 downto 16);
      when 114 => data_out_i <= reg_hr_b1(15 downto 8);
      when 115 => data_out_i <= reg_hr_b1(7 downto 0);
      when 116 => data_out_i <= reg_hr_b2(31 downto 24);
      when 117 => data_out_i <= reg_hr_b2(23 downto 16);
      when 118 => data_out_i <= reg_hr_b2(15 downto 8);
      when 119 => data_out_i <= reg_hr_b2(7 downto 0);
      when 120 => data_out_i <= reg_hr_b3(31 downto 24);
      when 121 => data_out_i <= reg_hr_b3(23 downto 16);
      when 122 => data_out_i <= reg_hr_b3(15 downto 8);
      when 123 => data_out_i <= reg_hr_b3(7 downto 0);
      when 124 => data_out_i <= reg_hr_b4(31 downto 24);
      when 125 => data_out_i <= reg_hr_b4(23 downto 16);
      when 126 => data_out_i <= reg_hr_b4(15 downto 8);
      when 127 => data_out_i <= reg_hr_b4(7 downto 0);
      when 128 => data_out_i <= reg_hr_b5(31 downto 24);
      when 129 => data_out_i <= reg_hr_b5(23 downto 16);
      when 130 => data_out_i <= reg_hr_b5(15 downto 8);
      when 131 => data_out_i <= reg_hr_b5(7 downto 0);
      when 132 => data_out_i <= reg_hr_b6(31 downto 24);
      when 133 => data_out_i <= reg_hr_b6(23 downto 16);
      when 134 => data_out_i <= reg_hr_b6(15 downto 8);
      when 135 => data_out_i <= reg_hr_b6(7 downto 0);
      when 136 => data_out_i <= reg_hr_b7(31 downto 24);
      when 137 => data_out_i <= reg_hr_b7(23 downto 16);
      when 138 => data_out_i <= reg_hr_b7(15 downto 8);
      when 139 => data_out_i <= reg_hr_b7(7 downto 0);
      when 140 => data_out_i <= reg_hr_b8(31 downto 24);
      when 141 => data_out_i <= reg_hr_b8(23 downto 16);
      when 142 => data_out_i <= reg_hr_b8(15 downto 8);
      when 143 => data_out_i <= reg_hr_b8(7 downto 0);
      when 144 => data_out_i <= reg_algo(31 downto 24);
      when 145 => data_out_i <= reg_algo(23 downto 16);
      when 146 => data_out_i <= reg_algo(15 downto 8);
      when 147 => data_out_i <= reg_algo(7 downto 0);
      when 148 => data_out_i <= reg_hr_c1(31 downto 24);
      when 149 => data_out_i <= reg_hr_c1(23 downto 16);
      when 150 => data_out_i <= reg_hr_c1(15 downto 8);
      when 151 => data_out_i <= reg_hr_c1(7 downto 0);
      when 152 => data_out_i <= reg_hr_c2(31 downto 24);
      when 153 => data_out_i <= reg_hr_c2(23 downto 16);
      when 154 => data_out_i <= reg_hr_c2(15 downto 8);
      when 155 => data_out_i <= reg_hr_c2(7 downto 0);
      when 156 => data_out_i <= reg_hr_c3(31 downto 24);
      when 157 => data_out_i <= reg_hr_c3(23 downto 16);
      when 158 => data_out_i <= reg_hr_c3(15 downto 8);
      when 159 => data_out_i <= reg_hr_c3(7 downto 0);
      when 160 => data_out_i <= reg_hr_c4(31 downto 24);
      when 161 => data_out_i <= reg_hr_c4(23 downto 16);
      when 162 => data_out_i <= reg_hr_c4(15 downto 8);
      when 163 => data_out_i <= reg_hr_c4(7 downto 0);
      when 164 => data_out_i <= reg_hr_c5(31 downto 24);
      when 165 => data_out_i <= reg_hr_c5(23 downto 16);
      when 166 => data_out_i <= reg_hr_c5(15 downto 8);
      when 167 => data_out_i <= reg_hr_c5(7 downto 0);
      when 168 => data_out_i <= reg_hr_c6(31 downto 24);
      when 169 => data_out_i <= reg_hr_c6(23 downto 16);
      when 170 => data_out_i <= reg_hr_c6(15 downto 8);
      when 171 => data_out_i <= reg_hr_c6(7 downto 0);
      when 172 => data_out_i <= reg_hr_c7(31 downto 24);
      when 173 => data_out_i <= reg_hr_c7(23 downto 16);
      when 174 => data_out_i <= reg_hr_c7(15 downto 8);
      when 175 => data_out_i <= reg_hr_c7(7 downto 0);
      when 176 => data_out_i <= reg_hr_c8(31 downto 24);
      when 177 => data_out_i <= reg_hr_c8(23 downto 16);
      when 178 => data_out_i <= reg_hr_c8(15 downto 8);
      when 179 => data_out_i <= reg_hr_c8(7 downto 0);
      when 180 => data_out_i <= reg_hr_d1(31 downto 24);
      when 181 => data_out_i <= reg_hr_d1(23 downto 16);
      when 182 => data_out_i <= reg_hr_d1(15 downto 8);
      when 183 => data_out_i <= reg_hr_d1(7 downto 0);
      when 184 => data_out_i <= reg_hr_d2(31 downto 24);
      when 185 => data_out_i <= reg_hr_d2(23 downto 16);
      when 186 => data_out_i <= reg_hr_d2(15 downto 8);
      when 187 => data_out_i <= reg_hr_d2(7 downto 0);
      when 188 => data_out_i <= reg_hr_d3(31 downto 24);
      when 189 => data_out_i <= reg_hr_d3(23 downto 16);
      when 190 => data_out_i <= reg_hr_d3(15 downto 8);
      when 191 => data_out_i <= reg_hr_d3(7 downto 0);
      when 192 => data_out_i <= reg_hr_d4(31 downto 24);
      when 193 => data_out_i <= reg_hr_d4(23 downto 16);
      when 194 => data_out_i <= reg_hr_d4(15 downto 8);
      when 195 => data_out_i <= reg_hr_d4(7 downto 0);
      when 196 => data_out_i <= reg_hr_d5(31 downto 24);
      when 197 => data_out_i <= reg_hr_d5(23 downto 16);
      when 198 => data_out_i <= reg_hr_d5(15 downto 8);
      when 199 => data_out_i <= reg_hr_d5(7 downto 0);
      when 200 => data_out_i <= reg_hr_d6(31 downto 24);
      when 201 => data_out_i <= reg_hr_d6(23 downto 16);
      when 202 => data_out_i <= reg_hr_d6(15 downto 8);
      when 203 => data_out_i <= reg_hr_d6(7 downto 0);
      when 204 => data_out_i <= reg_hr_d7(31 downto 24);
      when 205 => data_out_i <= reg_hr_d7(23 downto 16);
      when 206 => data_out_i <= reg_hr_d7(15 downto 8);
      when 207 => data_out_i <= reg_hr_d7(7 downto 0);
      when 208 => data_out_i <= reg_hr_d8(31 downto 24);
      when 209 => data_out_i <= reg_hr_d8(23 downto 16);
      when 210 => data_out_i <= reg_hr_d8(15 downto 8);
      when 211 => data_out_i <= reg_hr_d8(7 downto 0);
                  done_i <= '1';
      when others => data_out_i <= (others => '0');
                     done_i <= '0';
    end case;
  end process byte_assembly;

  DATA_OUT <= data_out_i when rising_edge(EMAC_CLK);

end status_collector_arc;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:05 2008 for BCM-AAA by  1.5.7.1-20081012