1.5.7.1-2008101200001 --************************************************************** 00002 --* * 00003 --* The source code for the ATLAS BCM "AAA" FPGA is made * 00004 --* available via the GNU General Public License (GPL) * 00005 --* unless otherwise stated below. * 00006 --* * 00007 --* In case of problems/questions/bug reports etc. please * 00008 --* contact michael.niegl@cern.ch * 00009 --* * 00010 --************************************************************** 00011 00012 --************************************************************** 00013 --* * 00014 --* $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/eth/command_decoder.vhd,v $ 00015 --* $Revision: 2.32.2.5 $ * 00016 --* $Name: dev $ * 00017 --* $Author: mniegl $ * 00018 --* $Date: 2008/11/03 17:57:46 $ * 00019 00020 00021 --* * 00022 --************************************************************** 00023 00024 00025 library ieee; 00026 00027 use ieee.std_logic_1164.all; 00028 00029 use ieee.std_logic_arith.all; 00030 00031 use ieee.std_logic_unsigned.all; 00032 00033 00034 00035 00036 00037 entity command_decoder is 00038 port ( 00039 --general 00040 CLOCK_IN : in std_logic; 00041 RESET : in std_logic; 00042 --pc side 00043 ADDRESS_IN : in std_logic_vector(11 downto 0); 00044 DATA_IN : in std_logic_vector(7 downto 0); 00045 DATA_VALID_IN : in std_logic; 00046 --outputs 00047 MODE : out std_logic; 00048 FPGA_RESET : out std_logic; 00049 RIO_RESET : out std_logic_vector(7 downto 0); 00050 BUFFER_DUMP_START : out std_logic; 00051 BUFFER_DUMP_STOP : out std_logic; 00052 S_LINK_START : out std_logic; 00053 S_LINK_END : out std_logic; 00054 S_LINK_PAUSE : out std_logic; 00055 FILL_BUFFER : out std_logic; 00056 START_OF_RUN : out std_logic; 00057 POST_MORTEM : out std_logic; 00058 ADJ_TIME_0 : out integer range 0 to 64; 00059 ADJ_TIME_1 : out integer range 0 to 64; 00060 ADJ_TIME_2 : out integer range 0 to 64; 00061 ADJ_TIME_3 : out integer range 0 to 64; 00062 ADJ_TIME_4 : out integer range 0 to 64; 00063 ADJ_TIME_5 : out integer range 0 to 64; 00064 ADJ_TIME_6 : out integer range 0 to 64; 00065 ADJ_TIME_7 : out integer range 0 to 64; 00066 ADJ_TIME_PULSE : out std_logic_vector(7 downto 0); 00067 NUMBER_OF_BUNCHES : out integer range 0 to 127; 00068 ECR_COUNT : out std_logic_vector(7 downto 0); 00069 L1A_COUNT : out std_logic_vector(23 downto 0); 00070 DSS_ABORT : out std_logic; 00071 DSS_WARNING : out std_logic; 00072 BEAM_PERMIT : out std_logic; 00073 INJECTION_PERMIT : out std_logic; 00074 CTP_PATTERN : out std_logic_vector(9 downto 1); 00075 PARAMETERS_I_PULSE : out std_logic_vector(7 downto 0); 00076 RUN_NUMBER : out std_logic_vector(31 downto 0); 00077 RUN_NUMBER_PULSE : out std_logic; 00078 EVENT_TYPE : out std_logic_vector(31 downto 0); 00079 EVENT_TYPE_PULSE : out std_logic; 00080 BUSY_EXTERNAL : out std_logic; 00081 SOURCE_ID : out std_logic_vector(23 downto 0); 00082 SOURCE_ID_PULSE : out std_logic; 00083 ALGO_SELECT : out std_logic_vector(7 downto 0); 00084 ALGO_SELECT_PULSE : out std_logic; 00085 PACKET_ACK : out std_logic; 00086 RESET_COUNTERS : out std_logic; 00087 GET_STATUS : out std_logic; 00088 RESERVED : out std_logic_vector(7 downto 0); 00089 INPUT_MASK : out std_logic_vector(7 downto 0); 00090 INPUT_MASK_PULSE : out std_logic; 00091 PACKET_OK : out std_logic; 00092 PACKET_ERROR : out std_logic; 00093 PACKET_MISSED : out std_logic; 00094 FPGA_ID : out std_logic_vector(7 downto 0); 00095 FPGA_ID_PULSE : out std_logic; 00096 READ_TDAQ_STATUS : out std_logic; 00097 BUSY_EXTERNAL_CLR : out std_logic; 00098 LVL1_ACCEPT : out std_logic_vector(5 downto 0); 00099 LVL1_ACCEPT_PULSE : out std_logic; 00100 FORMAT_VER : out std_logic_vector(31 downto 0); 00101 FORMAT_VER_PULSE : out std_logic; 00102 L1TT : out std_logic_vector(7 downto 0); 00103 L1TT_PULSE : out std_logic; 00104 ORBIT_COUNTER : out std_logic_vector(31 downto 0); 00105 ORBIT_COUNTER_PULSE : out std_logic; 00106 INHIBIT_DELAY : out std_logic_vector(7 downto 0); 00107 INHIBIT_DELAY_PULSE : out std_logic; 00108 TRIGGER_DELAY : out std_logic_vector(7 downto 0); 00109 TRIGGER_DELAY_PULSE : out std_logic; 00110 LATENCY : out std_logic_vector(7 downto 0); 00111 LATENCY_PULSE : out std_logic; 00112 FORCE_BCR : out std_logic; 00113 FORCE_ECR : out std_logic; 00114 FORCE_LVL1 : out std_logic; 00115 COARSE_DELAY_0 : out std_logic_vector(7 downto 0); 00116 COARSE_DELAY_1 : out std_logic_vector(7 downto 0); 00117 COARSE_DELAY_2 : out std_logic_vector(7 downto 0); 00118 COARSE_DELAY_3 : out std_logic_vector(7 downto 0); 00119 COARSE_DELAY_4 : out std_logic_vector(7 downto 0); 00120 COARSE_DELAY_5 : out std_logic_vector(7 downto 0); 00121 COARSE_DELAY_6 : out std_logic_vector(7 downto 0); 00122 COARSE_DELAY_7 : out std_logic_vector(7 downto 0); 00123 COARSE_DELAY_PULSE : out std_logic_vector(7 downto 0); 00124 TTY_SOURCE : out std_logic; 00125 TTY_SOURCE_PULSE : out std_logic; 00126 DSSW_SOURCE : out std_logic; 00127 DSSW_SOURCE_PULSE : out std_logic; 00128 DSSA_SOURCE : out std_logic; 00129 DSSA_SOURCE_PULSE : out std_logic; 00130 CIBI_SOURCE : out std_logic; 00131 CIBI_SOURCE_PULSE : out std_logic; 00132 CIBB_SOURCE : out std_logic; 00133 CIBB_SOURCE_PULSE : out std_logic; 00134 ACK_DSSW : out std_logic; 00135 ACK_DSSA : out std_logic; 00136 ACK_CIBI : out std_logic; 00137 ACK_CIBB : out std_logic; 00138 CTP_SOURCE : out std_logic; 00139 CTP_SOURCE_PULSE : out std_logic; 00140 CUT_COIN_L : out std_logic_vector(7 downto 0); 00141 CUT_COIN_H : out std_logic_vector(7 downto 0); 00142 CUT_WIDE_L : out std_logic_vector(7 downto 0); 00143 CUT_WIDE_H : out std_logic_vector(7 downto 0); 00144 CUT_OUTA_L : out std_logic_vector(7 downto 0); 00145 CUT_OUTA_H : out std_logic_vector(7 downto 0); 00146 CUT_OUTC_L : out std_logic_vector(7 downto 0); 00147 CUT_OUTC_H : out std_logic_vector(7 downto 0); 00148 CUT_VLD : out std_logic_vector(7 downto 0) 00149 ); 00150 end command_decoder; 00151 00152 00153 00154 00155 00156 architecture command_decoder_arc of command_decoder is 00157 00158 signal cnt_i : integer range 0 to 31 := 0; 00159 signal module_selected_i : std_logic := '0'; 00160 signal Data_valid_i : std_logic := '0'; 00161 signal expert : std_logic := '0'; 00162 signal inhibit_n : std_logic := '0'; 00163 signal triggers_i : std_logic_vector(50 downto 0) := (others => '0'); 00164 signal Data_i : std_logic_vector(7 downto 0) := (others => '0'); 00165 signal Addr_i : std_logic_vector(2 downto 0) := (others => '0'); 00166 constant address_triggers : std_logic_vector(2 downto 0) := "000"; 00167 constant address_delays : std_logic_vector(2 downto 0) := "001"; 00168 constant address_parameters_I : std_logic_vector(2 downto 0) := "010"; 00169 constant address_run_number : std_logic_vector(2 downto 0) := "011"; 00170 constant address_source_id : std_logic_vector(2 downto 0) := "100"; 00171 constant address_reserved : std_logic_vector(2 downto 0) := "101"; 00172 constant address_parameters_III : std_logic_vector(2 downto 0) := "110"; 00173 constant address_coarse_delay : std_logic_vector(2 downto 0) := "111"; 00174 00175 begin 00176 00177 MODE <= not expert; 00178 RESERVED <= (others => '0'); 00179 00180 process(CLOCK_IN) 00181 begin 00182 if CLOCK_IN'event and CLOCK_IN = '1' then 00183 if RESET = '1' then 00184 module_selected_i <= '0'; 00185 Data_i <= (others => '0'); 00186 Data_valid_i <= '0'; 00187 Addr_i <= (others => '0'); 00188 inhibit_n <= '0'; 00189 else 00190 Data_i <= Data_In; 00191 Data_valid_i <= DATA_VALID_IN; 00192 Addr_i <= ADDRESS_IN(2 downto 0); 00193 inhibit_n <= expert or ADDRESS_IN(11); 00194 if ADDRESS_IN(10 downto 3) = "00000001" then 00195 module_selected_i <= '1'; 00196 else 00197 module_selected_i <= '0'; 00198 end if; 00199 end if; 00200 end if; 00201 end process; 00202 00203 --maping to ports 00204 FPGA_RESET <= triggers_i(0); 00205 BUFFER_DUMP_START <= triggers_i(1); 00206 BUFFER_DUMP_STOP <= triggers_i(2); 00207 S_LINK_START <= triggers_i(3) and inhibit_n; 00208 S_LINK_END <= triggers_i(4) and inhibit_n; 00209 S_LINK_PAUSE <= triggers_i(5) and inhibit_n; 00210 FILL_BUFFER <= triggers_i(6) and inhibit_n; 00211 START_OF_RUN <= triggers_i(7) and inhibit_n; 00212 RUN_NUMBER_PULSE <= triggers_i(8) and inhibit_n; 00213 EVENT_TYPE_PULSE <= triggers_i(9) and inhibit_n; 00214 SOURCE_ID_PULSE <= triggers_i(10) and inhibit_n; 00215 ALGO_SELECT_PULSE <= triggers_i(11) and inhibit_n; 00216 PACKET_ACK <= triggers_i(12) and inhibit_n; 00217 RESET_COUNTERS <= triggers_i(13); 00218 GET_STATUS <= triggers_i(14); 00219 INPUT_MASK_PULSE <= triggers_i(15); 00220 PACKET_OK <= triggers_i(16); 00221 PACKET_ERROR <= triggers_i(17); 00222 PACKET_MISSED <= triggers_i(18); 00223 READ_TDAQ_STATUS <= triggers_i(19) and inhibit_n; 00224 FPGA_ID_PULSE <= triggers_i(20); 00225 BUSY_EXTERNAL_CLR <= triggers_i(21) and inhibit_n; 00226 LVL1_ACCEPT_PULSE <= triggers_i(22) and inhibit_n; 00227 FORMAT_VER_PULSE <= triggers_i(23) and inhibit_n; 00228 L1TT_PULSE <= triggers_i(24) and inhibit_n; 00229 ORBIT_COUNTER_PULSE <= triggers_i(25) and inhibit_n; 00230 INHIBIT_DELAY_PULSE <= triggers_i(26) and inhibit_n; 00231 TRIGGER_DELAY_PULSE <= triggers_i(27) and inhibit_n; 00232 FORCE_BCR <= triggers_i(28) and inhibit_n; 00233 FORCE_ECR <= triggers_i(29) and inhibit_n; 00234 FORCE_LVL1 <= triggers_i(30) and inhibit_n; 00235 COARSE_DELAY_PULSE(7) <= triggers_i(38) and inhibit_n; 00236 COARSE_DELAY_PULSE(6) <= triggers_i(37) and inhibit_n; 00237 COARSE_DELAY_PULSE(5) <= triggers_i(36) and inhibit_n; 00238 COARSE_DELAY_PULSE(4) <= triggers_i(35) and inhibit_n; 00239 COARSE_DELAY_PULSE(3) <= triggers_i(34) and inhibit_n; 00240 COARSE_DELAY_PULSE(2) <= triggers_i(33) and inhibit_n; 00241 COARSE_DELAY_PULSE(1) <= triggers_i(32) and inhibit_n; 00242 COARSE_DELAY_PULSE(0) <= triggers_i(31) and inhibit_n; 00243 CTP_SOURCE_PULSE <= triggers_i(39) and inhibit_n; 00244 TTY_SOURCE_PULSE <= triggers_i(40) and inhibit_n; 00245 DSSW_SOURCE_PULSE <= triggers_i(41) and inhibit_n; 00246 DSSA_SOURCE_PULSE <= triggers_i(42) and inhibit_n; 00247 CIBI_SOURCE_PULSE <= triggers_i(43) and inhibit_n; 00248 CIBB_SOURCE_PULSE <= triggers_i(44) and inhibit_n; 00249 LATENCY_PULSE <= triggers_i(45) and inhibit_n; 00250 ACK_DSSW <= triggers_i(46); 00251 ACK_DSSA <= triggers_i(47); 00252 ACK_CIBI <= triggers_i(48); 00253 ACK_CIBB <= triggers_i(49); 00254 POST_MORTEM <= triggers_i(50) and inhibit_n; 00255 00256 --reading machine 00257 fsm_read_from_pc : process (CLOCK_IN) 00258 begin 00259 if CLOCK_IN'event and CLOCK_IN = '1' then 00260 if RESET = '1' then 00261 triggers_i <= (others => '0'); 00262 ADJ_TIME_PULSE <= (others => '0'); 00263 PARAMETERS_I_PULSE <= (others => '0'); 00264 RESERVED <= (others => '0'); 00265 RIO_RESET <= (others => '0'); 00266 CUT_VLD <= (others => '0'); 00267 BUSY_EXTERNAL <= '0'; 00268 expert <= '0'; 00269 else 00270 triggers_i <= (others => '0'); 00271 ADJ_TIME_PULSE <= (others => '0'); 00272 PARAMETERS_I_PULSE <= (others => '0'); 00273 RESERVED <= (others => '0'); 00274 RIO_RESET <= (others => '0'); 00275 CUT_VLD <= (others => '0'); 00276 DSS_ABORT <= '0'; 00277 DSS_WARNING <= '0'; 00278 BUSY_EXTERNAL <= '0'; 00279 BEAM_PERMIT <= '1'; 00280 INJECTION_PERMIT <= '1'; 00281 00282 00283 if module_selected_i = '1' then --module is selected 00284 if data_valid_i = '1' then 00285 cnt_i <= cnt_i + 1; 00286 00287 case Addr_i is 00288 when address_triggers => --we are setting the triggers 00289 case cnt_i is 00290 when 0 => triggers_i(7 downto 0) <= Data_i; 00291 when 1 => RIO_RESET <= Data_i; 00292 when 2 => LATENCY <= Data_i; 00293 when 3 => cnt_i <= 0; 00294 triggers_i(45) <= Data_i(0); 00295 triggers_i(46) <= Data_i(1); 00296 triggers_i(47) <= Data_i(2); 00297 triggers_i(48) <= Data_i(3); 00298 triggers_i(49) <= Data_i(4); 00299 triggers_i(50) <= Data_i(5); 00300 when others => null; 00301 end case; 00302 00303 when address_delays => --we are setting the delays 00304 case cnt_i is 00305 when 0 => ADJ_TIME_0 <= CONV_INTEGER(Data_i); 00306 when 1 => ADJ_TIME_1 <= CONV_INTEGER(Data_i); 00307 when 2 => ADJ_TIME_2 <= CONV_INTEGER(Data_i); 00308 when 3 => ADJ_TIME_3 <= CONV_INTEGER(Data_i); 00309 when 4 => ADJ_TIME_4 <= CONV_INTEGER(Data_i); 00310 when 5 => ADJ_TIME_5 <= CONV_INTEGER(Data_i); 00311 when 6 => ADJ_TIME_6 <= CONV_INTEGER(Data_i); 00312 when 7 => ADJ_TIME_7 <= CONV_INTEGER(Data_i); 00313 when 8 => 00314 if inhibit_n = '1' then 00315 ADJ_TIME_PULSE <= Data_i; 00316 else 00317 ADJ_TIME_PULSE <= (others => '0'); 00318 end if; 00319 when 9 => CUT_COIN_L <= Data_i; 00320 when 10 => CUT_COIN_H <= Data_i; 00321 when 11 => CUT_WIDE_L <= Data_i; 00322 when 12 => CUT_WIDE_H <= Data_i; 00323 when 13 => CUT_OUTA_L <= Data_i; 00324 when 14 => CUT_OUTA_H <= Data_i; 00325 when 15 => CUT_OUTC_L <= Data_i; 00326 when 16 => CUT_OUTC_H <= Data_i; 00327 when 17 => 00328 if inhibit_n = '1' then 00329 CUT_VLD <= Data_i; 00330 else 00331 CUT_VLD <= (others => '0'); 00332 end if; 00333 cnt_i <= 0; 00334 when others => null; 00335 end case; 00336 00337 when address_parameters_I => --we are setting the parameters I 00338 if inhibit_n = '1' then 00339 case cnt_i is 00340 when 0 => NUMBER_OF_BUNCHES <= CONV_INTEGER(Data_i); 00341 when 1 => ECR_COUNT <= Data_i; 00342 when 2 => L1A_COUNT(23 downto 16) <= Data_i; 00343 when 3 => L1A_COUNT(15 downto 8) <= Data_i; 00344 when 4 => L1A_COUNT(7 downto 0) <= Data_i; 00345 when 5 => DSS_ABORT <= Data_i(7); 00346 DSS_WARNING <= Data_i(6); 00347 BEAM_PERMIT <= Data_i(5); 00348 INJECTION_PERMIT <= Data_i(4); 00349 triggers_i(21) <= Data_i(2); 00350 BUSY_EXTERNAL <= Data_i(1); 00351 CTP_PATTERN(9) <= Data_i(0); 00352 when 6 => CTP_PATTERN(8 downto 1) <= Data_i; 00353 when 7 => PARAMETERS_I_PULSE <= Data_i; 00354 cnt_i <= 0; 00355 when others => null; 00356 end case; 00357 end if; 00358 00359 when address_run_number => --we are setting run number and detector event type 00360 case cnt_i is 00361 when 0 => RUN_NUMBER(31 downto 24) <= '0' & Data_i(6 downto 0); 00362 when 1 => RUN_NUMBER(23 downto 16) <= Data_i; 00363 when 2 => RUN_NUMBER(15 downto 8) <= Data_i; 00364 when 3 => RUN_NUMBER(7 downto 0) <= Data_i; 00365 when 4 => EVENT_TYPE(31 downto 24) <= Data_i; 00366 when 5 => EVENT_TYPE(23 downto 16) <= Data_i; 00367 when 6 => EVENT_TYPE(15 downto 8) <= Data_i; 00368 when 7 => EVENT_TYPE(7 downto 0) <= Data_i; 00369 when 8 => TTY_SOURCE <= Data_i(0); 00370 when 9 => DSSW_SOURCE <= Data_i(0); 00371 when 10 => DSSA_SOURCE <= Data_i(0); 00372 when 11 => CIBI_SOURCE <= Data_i(0); 00373 when 12 => CIBB_SOURCE <= Data_i(0); 00374 when 13 => triggers_i(9 downto 8) <= Data_i(1 downto 0); 00375 triggers_i(44 downto 40) <= Data_i(6 downto 2); 00376 cnt_i <= 0; 00377 when others => null; 00378 end case; 00379 00380 when address_source_id => --we are setting source id and algorithm selection 00381 case cnt_i is 00382 when 0 => SOURCE_ID(23 downto 16) <= Data_i; 00383 when 1 => SOURCE_ID(15 downto 8) <= Data_i; 00384 when 2 => SOURCE_ID(7 downto 0) <= Data_i; 00385 when 3 => ALGO_SELECT <= Data_i; 00386 when 4 => INPUT_MASK <= Data_i; 00387 when 5 => triggers_i(15 downto 10) <= Data_i(5 downto 0); 00388 if inhibit_n = '1' then 00389 CTP_SOURCE <= Data_i(6); 00390 end if; 00391 triggers_i(39) <= Data_i(7); 00392 cnt_i <= 0; 00393 when others => null; 00394 end case; 00395 00396 when address_reserved => --we are setting reserved extra bits 00397 case cnt_i is 00398 when 0 => FPGA_ID <= Data_i; 00399 when 1 => 00400 triggers_i(19) <= Data_i(7) and Data_i(6) and Data_i(5) and Data_i(4) and 00401 Data_i(3) and Data_i(2) and Data_i(1) and Data_i(0); 00402 when 2 => 00403 if Data_i = x"ff" then 00404 expert <= '1'; 00405 elsif Data_i = x"11" then 00406 expert <= '0'; 00407 else 00408 expert <= expert; 00409 end if; 00410 when 3 => 00411 if Data_i = x"00" then 00412 triggers_i(18) <= '1'; 00413 elsif Data_i = x"0f" then 00414 triggers_i(17) <= '1'; 00415 elsif Data_i = x"ff" then 00416 triggers_i(16) <= '1'; 00417 elsif Data_i = x"11" then 00418 triggers_i(20) <= '1'; 00419 end if; 00420 cnt_i <= 0; 00421 when others => null; 00422 end case; 00423 00424 when address_parameters_III => 00425 case cnt_i is 00426 when 0 => LVL1_ACCEPT <= Data_i(7 downto 2); 00427 triggers_i(28) <= Data_i(1); 00428 triggers_i(29) <= Data_i(0); 00429 when 1 => FORMAT_VER(31 downto 24) <= Data_i; 00430 when 2 => FORMAT_VER(23 downto 16) <= Data_i; 00431 when 3 => FORMAT_VER(15 downto 8) <= Data_i; 00432 when 4 => FORMAT_VER(7 downto 0) <= Data_i; 00433 when 5 => L1TT <= Data_i; 00434 when 6 => ORBIT_COUNTER(31 downto 24) <= Data_i; 00435 when 7 => ORBIT_COUNTER(23 downto 16) <= Data_i; 00436 when 8 => ORBIT_COUNTER(15 downto 8) <= Data_i; 00437 when 9 => ORBIT_COUNTER(7 downto 0) <= Data_i; 00438 when 10 => INHIBIT_DELAY <= Data_i; 00439 when 11 => TRIGGER_DELAY <= Data_i; 00440 when 12 => triggers_i(30) <= Data_i(0); 00441 triggers_i(27 downto 22) <= Data_i(6 downto 1); 00442 cnt_i <= 0; 00443 when others => null; 00444 end case; 00445 00446 when address_coarse_delay => 00447 case cnt_i is 00448 when 0 => COARSE_DELAY_0 <= Data_i; 00449 when 1 => COARSE_DELAY_1 <= Data_i; 00450 when 2 => COARSE_DELAY_2 <= Data_i; 00451 when 3 => COARSE_DELAY_3 <= Data_i; 00452 when 4 => COARSE_DELAY_4 <= Data_i; 00453 when 5 => COARSE_DELAY_5 <= Data_i; 00454 when 6 => COARSE_DELAY_6 <= Data_i; 00455 when 7 => COARSE_DELAY_7 <= Data_i; 00456 when 8 => triggers_i(38 downto 31) <= Data_i(7 downto 0); 00457 cnt_i <= 0; 00458 when others => null; 00459 end case; --cnt_i 00460 00461 when others => 00462 end case; --Addr_i 00463 end if; --Data_valid_i 00464 else --module is not selected 00465 cnt_i <= 0; 00466 end if; 00467 end if; 00468 end if; 00469 end process fsm_read_from_pc; 00470 00471 end command_decoder_arc;
1.5.7.1-20081012