BCM-AAA: tdaq_collector.vhd Source File

00001 --**************************************************************
00002 --*                                                            *
00003 --*     The source code for the ATLAS BCM "AAA" FPGA is made   *
00004 --*     available via the GNU General Public License (GPL)     *
00005 --*     unless otherwise stated below.                         *
00006 --*                                                            *
00007 --*     In case of problems/questions/bug reports etc. please  *
00008 --*     contact michael.niegl@cern.ch                          *
00009 --*                                                            *
00010 --**************************************************************
00011 
00012 --**************************************************************
00013 --*                                                            *
00014 --*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/div/tdaq_collector.vhd,v $
00015 --*  $Revision: 1.13.2.7 $                                          *
00016 --*  $Name: dev $                                                 *
00017 --*  $Author: mniegl $                                         *
00018 --*  $Date: 2008/11/03 17:57:45 $                              *
00019 
00020 
00021 --*                                                            *
00022 --**************************************************************
00023 
00024 
00025 library ieee;
00026 
00027 use ieee.std_logic_1164.all;
00028 
00029 use ieee.std_logic_arith.all;
00030 
00031 use ieee.std_logic_unsigned.all;
00032 
00033 
00034 
00035 
00036 
00037 
00038 entity tdaq_collector is
00039   
00040   port (
00041     EMAC_CLK            : in  std_logic;
00042     ROD_CLK             : in  std_logic;
00043     STATUS_CLK          : in  std_logic;
00044     RIO_CLK             : in  std_logic;
00045     RESET               : in  std_logic;
00046     START               : in  std_logic;
00047     FETCH_BYTE          : in  std_logic;
00048     FETCH_CHKSUM        : in  std_logic;
00049     FPGA_ID             : in  std_logic_vector(7 downto 0) := x"00";
00050     ERROR_CODE          : in  std_logic_vector(7 downto 0);
00051     INPUT_STATUS        : in  std_logic_vector(63 downto 0);
00052     DATA_SRC            : in  std_logic_vector(7 downto 0);
00053     COARSE_DELAY1       : in  std_logic_vector(7 downto 0);
00054     COARSE_DELAY2       : in  std_logic_vector(7 downto 0);
00055     COARSE_DELAY3       : in  std_logic_vector(7 downto 0);
00056     COARSE_DELAY4       : in  std_logic_vector(7 downto 0);
00057     COARSE_DELAY5       : in  std_logic_vector(7 downto 0);
00058     COARSE_DELAY6       : in  std_logic_vector(7 downto 0);
00059     COARSE_DELAY7       : in  std_logic_vector(7 downto 0);
00060     COARSE_DELAY8       : in  std_logic_vector(7 downto 0);
00061     FINE_DELAY1         : in  std_logic_vector(7 downto 0);
00062     FINE_DELAY2         : in  std_logic_vector(7 downto 0);
00063     FINE_DELAY3         : in  std_logic_vector(7 downto 0);
00064     FINE_DELAY4         : in  std_logic_vector(7 downto 0);
00065     FINE_DELAY5         : in  std_logic_vector(7 downto 0);
00066     FINE_DELAY6         : in  std_logic_vector(7 downto 0);
00067     FINE_DELAY7         : in  std_logic_vector(7 downto 0);
00068     FINE_DELAY8         : in  std_logic_vector(7 downto 0);
00069     BUSY                : in  std_logic_vector(7 downto 0);
00070     BUSY_EXT            : in  std_logic_vector(7 downto 0);
00071     SLINK_FULL          : in  std_logic_vector(7 downto 0);
00072     SLINK_DOWN          : in  std_logic_vector(7 downto 0);
00073     L1A                 : in  std_logic;
00074     L1A_FIFO_FULL       : in  std_logic;
00075     L1A_FIFO_EMPTY      : in  std_logic;
00076     TRIGGER_DELAY       : in  std_logic_vector(7 downto 0);
00077     EXT_EVENT_ID        : in  std_logic_vector(31 downto 0);
00078     ORBIT_ID            : in  std_logic_vector(31 downto 0);
00079     INHIBIT_DELAY       : in  std_logic_vector(7 downto 0);
00080     BCID                : in  std_logic_vector(31 downto 0);
00081     DETECTOR_EVENT_TYPE : in  std_logic_vector(31 downto 0);
00082     SOURCE_ID           : in  std_logic_vector(31 downto 0);
00083     FORMAT_V            : in  std_logic_vector(31 downto 0);
00084     RUN_NUMBER          : in  std_logic_vector(31 downto 0);
00085     TRIGGER_TYPE        : in  std_logic_vector(7 downto 0);
00086     CTP_OUT             : in  std_logic_vector(8 downto 0);
00087     CTP_FORCE           : in  std_logic_vector(8 downto 0);
00088     CTP_SEL             : in  std_logic_vector(7 downto 0);
00089     DSS_WARNING         : in  std_logic;
00090     DSS_ABORT           : in  std_logic;
00091     INJ_PERM            : in  std_logic;
00092     BEAM_PERM           : in  std_logic;
00093     NUM_BUNCH           : in  std_logic_vector(7 downto 0);
00094     TTY_SEL             : in  std_logic_vector(7 downto 0);
00095     DSSA_SEL            : in  std_logic_vector(7 downto 0);
00096     DSSW_SEL            : in  std_logic_vector(7 downto 0);
00097     CIBI_SEL            : in  std_logic_vector(7 downto 0);
00098     CIBB_SEL            : in  std_logic_vector(7 downto 0);
00099     RX_LOCK             : in  std_logic_vector(7 downto 0);
00100     TX_LOCK             : in  std_logic_vector(7 downto 0);
00101     RX_READY            : in  std_logic_vector(7 downto 0);
00102     TX_READY            : in  std_logic_vector(7 downto 0);
00103     LATENCY             : in  std_logic_vector(7 downto 0);
00104     CUT_COIN_L          : in  std_logic_vector(7 downto 0);
00105     CUT_COIN_H          : in  std_logic_vector(7 downto 0);
00106     CUT_WIDE_L          : in  std_logic_vector(7 downto 0);
00107     CUT_WIDE_H          : in  std_logic_vector(7 downto 0);
00108     CUT_OUTA_L          : in  std_logic_vector(7 downto 0);
00109     CUT_OUTA_H          : in  std_logic_vector(7 downto 0);
00110     CUT_OUTC_L          : in  std_logic_vector(7 downto 0);
00111     CUT_OUTC_H          : in  std_logic_vector(7 downto 0);
00112     TRATE_AttC          : in  std_logic_vector(31 downto 0);
00113     TRATE_AttA          : in  std_logic_vector(31 downto 0);
00114     TRATE_Mult3pC       : in  std_logic_vector(31 downto 0);
00115     TRATE_Mult2C        : in  std_logic_vector(31 downto 0);
00116     TRATE_Mult1C        : in  std_logic_vector(31 downto 0);
00117     TRATE_Mult3pA       : in  std_logic_vector(31 downto 0);
00118     TRATE_Mult2A        : in  std_logic_vector(31 downto 0);
00119     TRATE_Mult1A        : in  std_logic_vector(31 downto 0);
00120     TRATE_Wide          : in  std_logic_vector(31 downto 0);
00121     TRATE_CtoA          : in  std_logic_vector(31 downto 0);
00122     TRATE_AtoC          : in  std_logic_vector(31 downto 0);
00123     TRANS_DONE          : out std_logic;
00124     ASM_DONE            : out std_logic;
00125     CHKSUM_OUT          : out std_logic_vector(15 downto 0);
00126     DATA_OUT            : out std_logic_vector(7 downto 0)
00127     );
00128 
00129 end tdaq_collector;
00130 
00131 
00132 
00133 
00134 
00135 
00136 architecture tdaq_collector_arc of tdaq_collector is
00137 
00138 
00139   component edge
00140     port(
00141       CLK   : in  std_logic;
00142       A     : in  std_logic;
00143       PULSE : out std_logic
00144       );
00145   end component;
00146 
00147 
00148   component ddr2_chksum_cal
00149     port(
00150       CLK        : in  std_logic;
00151       RESET      : in  std_logic;
00152       EN         : in  std_logic;
00153       DATA_IN    : in  std_logic_vector(127 downto 0);
00154       WRITE_DONE : in  std_logic;
00155       READ_DATA  : in  std_logic;
00156       CAL_COMPL  : out std_logic;
00157       DATA_OUT   : out std_logic_vector(15 downto 0)
00158       );
00159   end component;
00160 
00161   signal en_wr          : std_logic                      := '0';
00162   signal en_asm         : std_logic                      := '0';
00163   signal en_cal         : std_logic                      := '0';
00164   signal en_calfsm      : std_logic                      := '0';
00165   signal done_i         : std_logic                      := '0';
00166   signal cal_wr_done    : std_logic                      := '0';
00167   signal cal_done       : std_logic                      := '0';
00168   signal start_p_i      : std_logic                      := '0';
00169   signal start_del      : std_logic                      := '0';
00170   signal chksum_out_i   : std_logic_vector(15 downto 0)  := (others => '0');
00171   signal chk_in         : std_logic_vector(127 downto 0) := (others => '0');
00172   signal reg_fpga_id    : std_logic_vector(7 downto 0)   := (others => '0');
00173   signal reg_error      : std_logic_vector(7 downto 0)   := (others => '0');
00174   signal reg_mask       : std_logic_vector(63 downto 0)  := (others => '0');
00175   signal reg_datsrc     : std_logic_vector(7 downto 0)   := (others => '0');
00176   signal reg_coarse     : std_logic_vector(63 downto 0)  := (others => '0');
00177   signal reg_fine       : std_logic_vector(63 downto 0)  := (others => '0');
00178   signal reg_busy       : std_logic_vector(7 downto 0)   := (others => '0');
00179   signal reg_busyext    : std_logic_vector(7 downto 0)   := (others => '0');
00180   signal reg_lfull      : std_logic_vector(7 downto 0)   := (others => '0');
00181   signal reg_ldown      : std_logic_vector(7 downto 0)   := (others => '0');
00182   signal reg_l1a        : std_logic_vector(7 downto 0)   := (others => '0');
00183   signal reg_l1a_full   : std_logic_vector(7 downto 0)   := (others => '0');
00184   signal reg_l1a_empty  : std_logic_vector(7 downto 0)   := (others => '0');
00185   signal reg_trigdel    : std_logic_vector(7 downto 0)   := (others => '0');
00186   signal reg_ext_evt_id : std_logic_vector(31 downto 0)  := (others => '0');
00187   signal reg_orbit      : std_logic_vector(31 downto 0)  := (others => '0');
00188   signal reg_inhdel     : std_logic_vector(7 downto 0)   := (others => '0');
00189   signal reg_bcid       : std_logic_vector(31 downto 0)  := (others => '0');
00190   signal reg_dtet       : std_logic_vector(31 downto 0)  := (others => '0');
00191   signal reg_srcid      : std_logic_vector(31 downto 0)  := (others => '0');
00192   signal reg_formatv    : std_logic_vector(31 downto 0)  := (others => '0');
00193   signal reg_runno      : std_logic_vector(31 downto 0)  := (others => '0');
00194   signal reg_tty        : std_logic_vector(7 downto 0)   := (others => '0');
00195   signal reg_ctpout     : std_logic_vector(31 downto 0)  := (others => '0');
00196   signal reg_ctpfrc     : std_logic_vector(31 downto 0)  := (others => '0');
00197   signal reg_ctpsel     : std_logic_vector(7 downto 0)   := (others => '0');
00198   signal reg_dssw       : std_logic_vector(7 downto 0)   := (others => '0');
00199   signal reg_dssa       : std_logic_vector(7 downto 0)   := (others => '0');
00200   signal reg_inj        : std_logic_vector(7 downto 0)   := (others => '0');
00201   signal reg_beam       : std_logic_vector(7 downto 0)   := (others => '0');
00202   signal reg_numbunch   : std_logic_vector(7 downto 0)   := (others => '0');
00203   signal reg_ttysel     : std_logic_vector(7 downto 0)   := (others => '0');
00204   signal reg_dssasel    : std_logic_vector(7 downto 0)   := (others => '0');
00205   signal reg_dsswsel    : std_logic_vector(7 downto 0)   := (others => '0');
00206   signal reg_cibisel    : std_logic_vector(7 downto 0)   := (others => '0');
00207   signal reg_cibbsel    : std_logic_vector(7 downto 0)   := (others => '0');
00208   signal reg_rxlock     : std_logic_vector(7 downto 0)   := (others => '0');
00209   signal reg_txlock     : std_logic_vector(7 downto 0)   := (others => '0');
00210   signal reg_rxready    : std_logic_vector(7 downto 0)   := (others => '0');
00211   signal reg_txready    : std_logic_vector(7 downto 0)   := (others => '0');
00212   signal reg_latcy      : std_logic_vector(7 downto 0)   := (others => '0');
00213   signal reg_cut1       : std_logic_vector(7 downto 0)   := (others => '0');
00214   signal reg_cut2       : std_logic_vector(7 downto 0)   := (others => '0');
00215   signal reg_cut3       : std_logic_vector(7 downto 0)   := (others => '0');
00216   signal reg_cut4       : std_logic_vector(7 downto 0)   := (others => '0');
00217   signal reg_cut5       : std_logic_vector(7 downto 0)   := (others => '0');
00218   signal reg_cut6       : std_logic_vector(7 downto 0)   := (others => '0');
00219   signal reg_cut7       : std_logic_vector(7 downto 0)   := (others => '0');
00220   signal reg_cut8       : std_logic_vector(7 downto 0)   := (others => '0');
00221   signal reg_rAttC      : std_logic_vector(31 downto 0)  := (others => '0');
00222   signal reg_rAttA      : std_logic_vector(31 downto 0)  := (others => '0');
00223   signal reg_rMult3pC   : std_logic_vector(31 downto 0)  := (others => '0');
00224   signal reg_rMult2C    : std_logic_vector(31 downto 0)  := (others => '0');
00225   signal reg_rMult1C    : std_logic_vector(31 downto 0)  := (others => '0');
00226   signal reg_rMult3pA   : std_logic_vector(31 downto 0)  := (others => '0');
00227   signal reg_rMult2A    : std_logic_vector(31 downto 0)  := (others => '0');
00228   signal reg_rMult1A    : std_logic_vector(31 downto 0)  := (others => '0');
00229   signal reg_rWide      : std_logic_vector(31 downto 0)  := (others => '0');
00230   signal reg_rCtoA      : std_logic_vector(31 downto 0)  := (others => '0');
00231   signal reg_rAtoC      : std_logic_vector(31 downto 0)  := (others => '0');
00232   signal DATA_OUT_i     : std_logic_vector(7 downto 0)   := (others => '0');
00233 
00234 begin  -- tdaq_collector_arc
00235 
00236 
00237   start_pulse : edge
00238     port map(
00239       CLK   => EMAC_CLK ,
00240       A     => START ,
00241       PULSE => start_p_i 
00242       );
00243 
00244   start_del  <= START when rising_edge(EMAC_CLK);
00245   TRANS_DONE <= done_i;
00246   ASM_DONE   <= cal_done;
00247 
00248 
00249   latch_enable_assembly : process (EMAC_CLK, RESET)
00250   begin  -- process latch_enable_assembly
00251     if RESET = '1' then                 -- asynchronous reset (active high)
00252       en_asm <= '0';
00253     elsif EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
00254       if start_del = '1' then
00255         en_asm <= '1';
00256       elsif done_i = '1' then
00257         en_asm <= '0';
00258       end if;
00259     end if;
00260   end process latch_enable_assembly;
00261 
00262 
00263   latch_enable_calculation : process (EMAC_CLK, RESET)
00264   begin  -- process latch_enable_assembly
00265     if RESET = '1' then                 -- asynchronous reset (active high)
00266       en_calfsm <= '0';
00267     elsif EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
00268       if start_p_i = '1' then
00269         en_calfsm <= '1';
00270       elsif cal_wr_done = '1' then
00271         en_calfsm <= '0';
00272       end if;
00273     end if;
00274   end process latch_enable_calculation;
00275 
00276   en_wr <= not en_asm;
00277 
00278 
00279   reg_ctpout(31 downto 9) <= (others => '0');
00280   reg_ctpfrc(31 downto 9) <= (others => '0');
00281 
00282 
00283   registers_40 : process (ROD_CLK, RESET)
00284   begin  -- process registers
00285     if RESET = '1' then                 -- asynchronous reset (active high)
00286       reg_coarse             <= (others => '0');
00287       reg_datsrc             <= (others => '0');
00288       reg_fine               <= (others => '0');
00289       reg_busy               <= (others => '0');
00290       reg_busyext            <= (others => '0');
00291       reg_lfull              <= (others => '0');
00292       reg_ldown              <= (others => '0');
00293       reg_l1a                <= (others => '0');
00294       reg_l1a_full           <= (others => '0');
00295       reg_l1a_empty          <= (others => '0');
00296       reg_trigdel            <= (others => '0');
00297       reg_ext_evt_id         <= (others => '0');
00298       reg_orbit              <= (others => '0');
00299       reg_inhdel             <= (others => '0');
00300       reg_bcid               <= (others => '0');
00301       reg_dtet               <= (others => '0');
00302       reg_srcid              <= (others => '0');
00303       reg_formatv            <= (others => '0');
00304       reg_runno              <= (others => '0');
00305       reg_tty                <= (others => '0');
00306       reg_ctpout(8 downto 0) <= (others => '0');
00307       reg_ctpfrc(8 downto 0) <= (others => '0');
00308       reg_ctpsel             <= (others => '0');
00309       reg_ttysel             <= (others => '0');
00310       reg_dssasel            <= (others => '0');
00311       reg_dsswsel            <= (others => '0');
00312       reg_cibisel            <= (others => '0');
00313       reg_cibbsel            <= (others => '0');
00314       reg_dssw               <= (others => '0');
00315       reg_dssa               <= (others => '0');
00316       reg_inj                <= (others => '0');
00317       reg_beam               <= (others => '0');
00318       reg_latcy              <= (others => '0');
00319       reg_cut1               <= (others => '0');
00320       reg_cut2               <= (others => '0');
00321       reg_cut3               <= (others => '0');
00322       reg_cut4               <= (others => '0');
00323       reg_cut5               <= (others => '0');
00324       reg_cut6               <= (others => '0');
00325       reg_cut7               <= (others => '0');
00326       reg_cut8               <= (others => '0');
00327       reg_rAttC              <= (others => '0');
00328       reg_rAttA              <= (others => '0');
00329       reg_rMult3pC           <= (others => '0');
00330       reg_rMult2C            <= (others => '0');
00331       reg_rMult1C            <= (others => '0');
00332       reg_rMult3pA           <= (others => '0');
00333       reg_rMult2A            <= (others => '0');
00334       reg_rMult1A            <= (others => '0');
00335       reg_rWide              <= (others => '0');
00336       reg_rCtoA              <= (others => '0');
00337       reg_rAtoC              <= (others => '0');
00338     elsif ROD_CLK'event and ROD_CLK = '1' then
00339       if en_wr = '1' then
00340         reg_coarse <= COARSE_DELAY1 & COARSE_DELAY2 & COARSE_DELAY3 & COARSE_DELAY4 &
00341                       COARSE_DELAY5 & COARSE_DELAY6 & COARSE_DELAY7 & COARSE_DELAY8;
00342         reg_fine <= FINE_DELAY1 & FINE_DELAY2 & FINE_DELAY3 & FINE_DELAY4 &
00343                     FINE_DELAY5 & FINE_DELAY6 & FINE_DELAY7 & FINE_DELAY8;
00344         reg_datsrc             <= DATA_SRC;
00345         reg_busy               <= BUSY;
00346         reg_busyext            <= BUSY_EXT;
00347         reg_lfull              <= SLINK_FULL;
00348         reg_ldown              <= SLINK_DOWN;
00349         reg_trigdel            <= TRIGGER_DELAY;
00350         reg_ext_evt_id         <= EXT_EVENT_ID;
00351         reg_orbit              <= ORBIT_ID;
00352         reg_inhdel             <= INHIBIT_DELAY;
00353         reg_bcid               <= BCID;
00354         reg_dtet               <= DETECTOR_EVENT_TYPE;
00355         reg_srcid              <= SOURCE_ID;
00356         reg_formatv            <= FORMAT_V;
00357         reg_runno              <= RUN_NUMBER;
00358         reg_tty                <= TRIGGER_TYPE;
00359         reg_ctpout(8 downto 0) <= CTP_OUT;
00360         reg_ctpfrc(8 downto 0) <= CTP_FORCE;
00361         reg_ctpsel             <= CTP_SEL;
00362         reg_ttysel             <= TTY_SEL;
00363         reg_dsswsel            <= DSSW_SEL;
00364         reg_dssasel            <= DSSA_SEL;
00365         reg_cibisel            <= CIBI_SEL;
00366         reg_cibbsel            <= CIBB_SEL;
00367         reg_latcy              <= LATENCY;
00368         reg_cut1               <= CUT_COIN_L;
00369         reg_cut2               <= CUT_COIN_H;
00370         reg_cut3               <= CUT_WIDE_L;
00371         reg_cut4               <= CUT_WIDE_H;
00372         reg_cut5               <= CUT_OUTA_L;
00373         reg_cut6               <= CUT_OUTA_H;
00374         reg_cut7               <= CUT_OUTC_L;
00375         reg_cut8               <= CUT_OUTC_H;
00376         reg_rAttC              <= TRATE_AttC;
00377         reg_rAttA              <= TRATE_AttA;
00378         reg_rMult3pC           <= TRATE_Mult3pC;
00379         reg_rMult2C            <= TRATE_Mult2C;
00380         reg_rMult1C            <= TRATE_Mult1C;
00381         reg_rMult3pA           <= TRATE_Mult3pA;
00382         reg_rMult2A            <= TRATE_Mult2A;
00383         reg_rMult1A            <= TRATE_Mult1A;
00384         reg_rWide              <= TRATE_Wide;
00385         reg_rCtoA              <= TRATE_CtoA;
00386         reg_rAtoC              <= TRATE_AtoC;
00387         if INJ_PERM = '1' then
00388           reg_inj <= (others => '1');
00389         else
00390           reg_inj <= (others => '0');
00391         end if;
00392         if BEAM_PERM = '1' then
00393           reg_beam <= (others => '1');
00394         else
00395           reg_beam <= (others => '0');
00396         end if;
00397         if DSS_WARNING = '1' then
00398           reg_dssw <= (others => '1');
00399         else
00400           reg_dssw <= (others => '0');
00401         end if;
00402         if DSS_ABORT = '1' then
00403           reg_dssa <= (others => '1');
00404         else
00405           reg_dssa <= (others => '0');
00406         end if;
00407         if L1A = '1' then
00408           reg_l1a <= (others => '1');
00409         else
00410           reg_l1a <= (others => '0');
00411         end if;
00412         if L1A_FIFO_FULL = '1' then
00413           reg_l1a_full <= (others => '1');
00414         else
00415           reg_l1a_full <= (others => '0');
00416         end if;
00417         if L1A_FIFO_EMPTY = '1' then
00418           reg_l1a_empty <= (others => '1');
00419         else
00420           reg_l1a_empty <= (others => '0');
00421         end if;
00422       end if;
00423     end if;
00424   end process registers_40;
00425 
00426 
00427   registers_160 : process (RIO_CLK, RESET)
00428   begin  -- process registers
00429     if RESET = '1' then                 -- asynchronous reset (active high)
00430       reg_mask    <= (others => '0');
00431       reg_rxready <= (others => '0');
00432       reg_rxlock  <= (others => '0');
00433       reg_txready <= (others => '0');
00434       reg_txlock  <= (others => '0');
00435     elsif RIO_CLK'event and RIO_CLK = '1' then
00436       if en_wr = '1' then
00437         reg_mask    <= INPUT_STATUS;
00438         reg_rxlock  <= RX_LOCK;
00439         reg_rxready <= RX_READY;
00440         reg_txlock  <= TX_LOCK;
00441         reg_txready <= TX_READY;
00442       end if;
00443     end if;
00444   end process registers_160;
00445 
00446 
00447   registers_200 : process (STATUS_CLK, RESET)
00448   begin  -- process registers
00449     if RESET = '1' then                 -- asynchronous reset (active high)
00450       reg_error <= (others => '0');
00451     elsif STATUS_CLK'event and STATUS_CLK = '1' then
00452       if en_wr = '1' then
00453         reg_error <= ERROR_CODE;
00454       end if;
00455     end if;
00456   end process registers_200;
00457 
00458 
00459   registers_100 : process (EMAC_CLK, RESET)
00460   begin  -- process registers
00461     if RESET = '1' then                 -- asynchronous reset (active high)
00462       reg_fpga_id  <= (others => '0');
00463       reg_numbunch <= (others => '0');
00464     elsif EMAC_CLK'event and EMAC_CLK = '1' then
00465       if en_wr = '1' then
00466         reg_fpga_id  <= FPGA_ID;
00467         reg_numbunch <= NUM_BUNCH;
00468       end if;
00469     end if;
00470   end process registers_100;
00471 
00472 
00473   checksum_assembly : process (EMAC_CLK, RESET)
00474     variable cnt : integer range 0 to 31 := 0;
00475   begin  -- process checksum_assembly
00476     if RESET = '1' then                 -- asynchronous reset (active high)
00477       chk_in      <= (others => '0');
00478       en_cal      <= '0';
00479       cal_wr_done <= '0';
00480       cnt         := 0;
00481     elsif EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
00482       if en_calfsm = '1' then
00483         en_cal      <= '1';
00484         cal_wr_done <= '0';
00485         case cnt is
00486           when 0 => chk_in <= reg_fpga_id & reg_error & reg_mask & reg_datsrc & reg_coarse(63 downto 24);
00487           when 1 => chk_in <= reg_coarse(23 downto 0) & reg_fine & reg_busy & reg_busyext & reg_lfull &
00488                               reg_ldown & reg_l1a;
00489           when 2 => chk_in <= reg_l1a_full & reg_l1a_empty & reg_trigdel & reg_ext_evt_id &
00490                               reg_orbit & reg_inhdel & reg_bcid;
00491           when 3 => chk_in <= reg_dtet & reg_srcid & reg_formatv & reg_runno;
00492           when 4 => chk_in <= reg_tty & reg_ctpout & reg_ctpfrc & reg_ctpsel & reg_dssw & reg_dssa & reg_inj &
00493                               reg_beam & reg_numbunch & reg_ttysel;
00494           when 5 => chk_in <= reg_dsswsel & reg_dssasel & reg_cibisel & reg_cibbsel & reg_rxlock &
00495                               reg_txlock & reg_rxready & reg_txready & reg_latcy & reg_rAttC & reg_rAttA(31 downto 8);
00496           when 6 => chk_in <= reg_rAttA(7 downto 0) & reg_rMult3pC & reg_rMult2C & reg_rMult1C & reg_rMult3pA(31 downto 8);
00497           when 7 => chk_in <= reg_rMult3pA(7 downto 0) & reg_rMult2A & reg_rMult1A & reg_rWide & reg_rCtoA(31 downto 8);
00498           when 8 => chk_in <= reg_rCtoA(7 downto 0) & reg_rAtoC & x"00_00_00_00_00_00_00_00_00_00_00";
00499           when 9 => chk_in <= (others => '0');
00500                     cal_wr_done <= '1';
00501           when others => chk_in <= (others => '0');
00502                          cal_wr_done <= '0';
00503         end case;
00504         cnt := cnt + 1;
00505       else
00506         cnt         := 0;
00507         chk_in      <= (others => '0');
00508         cal_wr_done <= '0';
00509         en_cal      <= '0';
00510       end if;
00511     end if;
00512   end process checksum_assembly;
00513 
00514 
00515   chksum_cal : ddr2_chksum_cal
00516     port map(
00517       CLK         => EMAC_CLK,
00518       RESET      => RESET,
00519       EN          => en_cal,
00520       DATA_IN    => chk_in,
00521       WRITE_DONE => cal_wr_done,
00522       CAL_COMPL  => cal_done,
00523       READ_DATA  => FETCH_CHKSUM,
00524       DATA_OUT   => chksum_out_i
00525       );
00526 
00527   CHKSUM_OUT <= (others => '0') when RESET = '1' else chksum_out_i;
00528 
00529   byte_assembly : process (EMAC_CLK, RESET)
00530     variable ocnt : integer range 0 to 255 := 0;
00531   begin  -- process byte_assembly
00532     if RESET = '1' then                 -- asynchronous reset (active high)
00533       done_i     <= '0';
00534       ocnt       := 0;
00535       DATA_OUT_i <= (others => '0');
00536     elsif EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
00537       DATA_OUT <= DATA_OUT_i;
00538       if FETCH_BYTE = '1' then
00539         done_i <= '0';
00540         ocnt   := ocnt + 1;
00541         case ocnt is
00542           when 1   => DATA_OUT_i <= reg_fpga_id;
00543           when 2   => DATA_OUT_i <= reg_error;
00544           when 3   => DATA_OUT_i <= reg_mask(63 downto 56);
00545           when 4   => DATA_OUT_i <= reg_mask(55 downto 48);
00546           when 5   => DATA_OUT_i <= reg_mask(47 downto 40);
00547           when 6   => DATA_OUT_i <= reg_mask(39 downto 32);
00548           when 7   => DATA_OUT_i <= reg_mask(31 downto 24);
00549           when 8   => DATA_OUT_i <= reg_mask(23 downto 16);
00550           when 9   => DATA_OUT_i <= reg_mask(15 downto 8);
00551           when 10  => DATA_OUT_i <= reg_mask(7 downto 0);
00552           when 11  => DATA_OUT_i <= reg_datsrc;
00553           when 12  => DATA_OUT_i <= reg_coarse(63 downto 56);
00554           when 13  => DATA_OUT_i <= reg_coarse(55 downto 48);
00555           when 14  => DATA_OUT_i <= reg_coarse(47 downto 40);
00556           when 15  => DATA_OUT_i <= reg_coarse(39 downto 32);
00557           when 16  => DATA_OUT_i <= reg_coarse(31 downto 24);
00558           when 17  => DATA_OUT_i <= reg_coarse(23 downto 16);
00559           when 18  => DATA_OUT_i <= reg_coarse(15 downto 8);
00560           when 19  => DATA_OUT_i <= reg_coarse(7 downto 0);
00561           when 20  => DATA_OUT_i <= reg_fine(63 downto 56);
00562           when 21  => DATA_OUT_i <= reg_fine(55 downto 48);
00563           when 22  => DATA_OUT_i <= reg_fine(47 downto 40);
00564           when 23  => DATA_OUT_i <= reg_fine(39 downto 32);
00565           when 24  => DATA_OUT_i <= reg_fine(31 downto 24);
00566           when 25  => DATA_OUT_i <= reg_fine(23 downto 16);
00567           when 26  => DATA_OUT_i <= reg_fine(15 downto 8);
00568           when 27  => DATA_OUT_i <= reg_fine(7 downto 0);
00569           when 28  => DATA_OUT_i <= reg_busy;
00570           when 29  => DATA_OUT_i <= reg_busyext;
00571           when 30  => DATA_OUT_i <= reg_lfull;
00572           when 31  => DATA_OUT_i <= reg_ldown;
00573           when 32  => DATA_OUT_i <= reg_l1a;
00574           when 33  => DATA_OUT_i <= reg_l1a_full;
00575           when 34  => DATA_OUT_i <= reg_l1a_empty;
00576           when 35  => DATA_OUT_i <= reg_trigdel;
00577           when 36  => DATA_OUT_i <= reg_ext_evt_id(31 downto 24);
00578           when 37  => DATA_OUT_i <= reg_ext_evt_id(23 downto 16);
00579           when 38  => DATA_OUT_i <= reg_ext_evt_id(15 downto 8);
00580           when 39  => DATA_OUT_i <= reg_ext_evt_id(7 downto 0);
00581           when 40  => DATA_OUT_i <= reg_orbit(31 downto 24);
00582           when 41  => DATA_OUT_i <= reg_orbit(23 downto 16);
00583           when 42  => DATA_OUT_i <= reg_orbit(15 downto 8);
00584           when 43  => DATA_OUT_i <= reg_orbit(7 downto 0);
00585           when 44  => DATA_OUT_i <= reg_inhdel;
00586           when 45  => DATA_OUT_i <= reg_bcid(31 downto 24);
00587           when 46  => DATA_OUT_i <= reg_bcid(23 downto 16);
00588           when 47  => DATA_OUT_i <= reg_bcid(15 downto 8);
00589           when 48  => DATA_OUT_i <= reg_bcid(7 downto 0);
00590           when 49  => DATA_OUT_i <= reg_dtet(31 downto 24);
00591           when 50  => DATA_OUT_i <= reg_dtet(23 downto 16);
00592           when 51  => DATA_OUT_i <= reg_dtet(15 downto 8);
00593           when 52  => DATA_OUT_i <= reg_dtet(7 downto 0);
00594           when 53  => DATA_OUT_i <= reg_srcid(31 downto 24);
00595           when 54  => DATA_OUT_i <= reg_srcid(23 downto 16);
00596           when 55  => DATA_OUT_i <= reg_srcid(15 downto 8);
00597           when 56  => DATA_OUT_i <= reg_srcid(7 downto 0);
00598           when 57  => DATA_OUT_i <= reg_formatv(31 downto 24);
00599           when 58  => DATA_OUT_i <= reg_formatv(23 downto 16);
00600           when 59  => DATA_OUT_i <= reg_formatv(15 downto 8);
00601           when 60  => DATA_OUT_i <= reg_formatv(7 downto 0);
00602           when 61  => DATA_OUT_i <= reg_runno(31 downto 24);
00603           when 62  => DATA_OUT_i <= reg_runno(23 downto 16);
00604           when 63  => DATA_OUT_i <= reg_runno(15 downto 8);
00605           when 64  => DATA_OUT_i <= reg_runno(7 downto 0);
00606           when 65  => DATA_OUT_i <= reg_tty;
00607           when 66  => DATA_OUT_i <= reg_ctpout(31 downto 24);
00608           when 67  => DATA_OUT_i <= reg_ctpout(23 downto 16);
00609           when 68  => DATA_OUT_i <= reg_ctpout(15 downto 8);
00610           when 69  => DATA_OUT_i <= reg_ctpout(7 downto 0);
00611           when 70  => DATA_OUT_i <= reg_ctpfrc(31 downto 24);
00612           when 71  => DATA_OUT_i <= reg_ctpfrc(23 downto 16);
00613           when 72  => DATA_OUT_i <= reg_ctpfrc(15 downto 8);
00614           when 73  => DATA_OUT_i <= reg_ctpfrc(7 downto 0);
00615           when 74  => DATA_OUT_i <= reg_ctpsel;
00616           when 75  => DATA_OUT_i <= reg_dssw;
00617           when 76  => DATA_OUT_i <= reg_dssa;
00618           when 77  => DATA_OUT_i <= reg_inj;
00619           when 78  => DATA_OUT_i <= reg_beam;
00620           when 79  => DATA_OUT_i <= reg_numbunch;
00621           when 80  => DATA_OUT_i <= reg_ttysel;
00622           when 81  => DATA_OUT_i <= reg_dsswsel;
00623           when 82  => DATA_OUT_i <= reg_dssasel;
00624           when 83  => DATA_OUT_i <= reg_cibisel;
00625           when 84  => DATA_OUT_i <= reg_cibbsel;
00626           when 85  => DATA_OUT_i <= reg_rxlock;
00627           when 86  => DATA_OUT_i <= reg_txlock;
00628           when 87  => DATA_OUT_i <= reg_rxready;
00629           when 88  => DATA_OUT_i <= reg_txready;
00630           when 89  => DATA_OUT_i <= reg_latcy;
00631           when 90  => DATA_OUT_i <= reg_cut1;
00632           when 91  => DATA_OUT_i <= reg_cut2;
00633           when 92  => DATA_OUT_i <= reg_cut3;
00634           when 93  => DATA_OUT_i <= reg_cut4;
00635           when 94  => DATA_OUT_i <= reg_cut5;
00636           when 95  => DATA_OUT_i <= reg_cut6;
00637           when 96  => DATA_OUT_i <= reg_cut7;
00638           when 97  => DATA_OUT_i <= reg_cut8;
00639           when 98  => DATA_OUT_i <= reg_rAttC(31 downto 24);
00640           when 99  => DATA_OUT_i <= reg_rAttC(23 downto 16);
00641           when 100 => DATA_OUT_i <= reg_rAttC(15 downto 8);
00642           when 101 => DATA_OUT_i <= reg_rAttC(7 downto 0);
00643           when 102 => DATA_OUT_i <= reg_rAttA(31 downto 24);
00644           when 103 => DATA_OUT_i <= reg_rAttA(23 downto 16);
00645           when 104 => DATA_OUT_i <= reg_rAttA(15 downto 8);
00646           when 105 => DATA_OUT_i <= reg_rAttA(7 downto 0);
00647           when 106 => DATA_OUT_i <= reg_rMult3pC(31 downto 24);
00648           when 107 => DATA_OUT_i <= reg_rMult3pC(23 downto 16);
00649           when 108 => DATA_OUT_i <= reg_rMult3pC(15 downto 8);
00650           when 109 => DATA_OUT_i <= reg_rMult3pC(7 downto 0);
00651           when 110 => DATA_OUT_i <= reg_rMult2C(31 downto 24);
00652           when 111 => DATA_OUT_i <= reg_rMult2C(23 downto 16);
00653           when 112 => DATA_OUT_i <= reg_rMult2C(15 downto 8);
00654           when 113 => DATA_OUT_i <= reg_rMult2C(7 downto 0);
00655           when 114 => DATA_OUT_i <= reg_rMult1C(31 downto 24);
00656           when 115 => DATA_OUT_i <= reg_rMult1C(23 downto 16);
00657           when 116 => DATA_OUT_i <= reg_rMult1C(15 downto 8);
00658           when 117 => DATA_OUT_i <= reg_rMult1C(7 downto 0);
00659           when 118 => DATA_OUT_i <= reg_rMult3pA(31 downto 24);
00660           when 119 => DATA_OUT_i <= reg_rMult3pA(23 downto 16);
00661           when 120 => DATA_OUT_i <= reg_rMult3pA(15 downto 8);
00662           when 121 => DATA_OUT_i <= reg_rMult3pA(7 downto 0);
00663           when 122 => DATA_OUT_i <= reg_rMult2A(31 downto 24);
00664           when 123 => DATA_OUT_i <= reg_rMult2A(23 downto 16);
00665           when 124 => DATA_OUT_i <= reg_rMult2A(15 downto 8);
00666           when 125 => DATA_OUT_i <= reg_rMult2A(7 downto 0);
00667           when 126 => DATA_OUT_i <= reg_rMult1A(31 downto 24);
00668           when 127 => DATA_OUT_i <= reg_rMult1A(23 downto 16);
00669           when 128 => DATA_OUT_i <= reg_rMult1A(15 downto 8);
00670           when 129 => DATA_OUT_i <= reg_rMult1A(7 downto 0);
00671           when 130 => DATA_OUT_i <= reg_rWide(31 downto 24);
00672           when 131 => DATA_OUT_i <= reg_rWide(23 downto 16);
00673           when 132 => DATA_OUT_i <= reg_rWide(15 downto 8);
00674           when 133 => DATA_OUT_i <= reg_rWide(7 downto 0);
00675           when 134 => DATA_OUT_i <= reg_rCtoA(31 downto 24);
00676           when 135 => DATA_OUT_i <= reg_rCtoA(23 downto 16);
00677           when 136 => DATA_OUT_i <= reg_rCtoA(15 downto 8);
00678           when 137 => DATA_OUT_i <= reg_rCtoA(7 downto 0);
00679           when 138 => DATA_OUT_i <= reg_rAtoC(31 downto 24);
00680           when 139 => DATA_OUT_i <= reg_rAtoC(23 downto 16);
00681           when 140 => DATA_OUT_i <= reg_rAtoC(15 downto 8);
00682           when 141 => DATA_OUT_i <= reg_rAtoC(7 downto 0);
00683                       done_i <= '1';
00684           when others => DATA_OUT_i <= (others => '0');
00685         end case;
00686       else
00687         ocnt       := 0;
00688         DATA_OUT_i <= (others => '0');
00689       end if;
00690     end if;
00691   end process byte_assembly;
00692   
00693 end tdaq_collector_arc;