00001 --**************************************************************
00002 --* *
00003 --* The source code for the ATLAS BCM "AAA" FPGA is made *
00004 --* available via the GNU General Public License (GPL) *
00005 --* unless otherwise stated below. *
00006 --* *
00007 --* In case of problems/questions/bug reports etc. please *
00008 --* contact michael.niegl@cern.ch *
00009 --* *
00010 --**************************************************************
00011
00012 --**************************************************************
00013 --* *
00014 --* $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/coin/timewindow.vhd,v $
00015 --* $Revision: 1.3.2.6 $ *
00016 --* $Name: dev $ *
00017 --* $Author: mniegl $ *
00018 --* $Date: 2008/11/03 17:57:43 $ *
00019
00020
00021 --* *
00022 --**************************************************************
00023
00024 library ieee;
00025
00026 use ieee.std_logic_1164.all;
00027
00028 use ieee.std_logic_arith.all;
00029
00030 use ieee.std_logic_unsigned.all;
00031
00032
00033
00034
00035
00036
00037 entity timewindow is
00038 port (
00039 CLK : in ;
00040 UPPER : in (5 downto 0) := "101110";
00041 LOWER : in (5 downto 0) := "010000";
00042 VAL_IN : in (5 downto 0);
00043 VAL_OUT : out (5 downto 0);
00044 IN_TIME : out
00045 );
00046 end timewindow;
00047
00048
00049
00050
00051
00052
00053 architecture timewindow_arc of timewindow is
00054 -------------------------- signals -----------------------------
00055 signal res_up : := '0';
00056 signal res_dwn : := '0';
00057
00058 begin
00059
00060 res_up <= '1' when VAL_IN > LOWER else '0';
00061 res_dwn <= '1' when VAL_IN < UPPER else '0';
00062
00063 IN_TIME <= res_up and res_dwn;
00064 VAL_OUT <= VAL_IN;
00065
00066 end timewindow_arc;
00067