bcm_rod_ram.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/rod/bcm_rod_ram.vhd,v $                                                  *
--*  $Revision: 1.10.2.4 $                                         *
--*  $Name: dev $                                              *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:48 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;



entity bcm_rod_ram is
  port (
    CLK                   : in  std_logic;
    CLK_2X                : in  std_logic;
    SCLR                  : in  std_logic;
    data_input            : in  std_logic_vector(31 downto 0);
    data_input_valid      : in  std_logic;
    data_input_endoffrag  : in  std_logic;
    stop                  : in  std_logic;
    data_output_next      : in  std_logic;
    data_output           : out std_logic_vector(31 downto 0);
    data_output_vld       : out std_logic;
    data_output_available : out std_logic;
    data_output_endoffrag : out std_logic;
    busy                  : out std_logic;
    write_error           : out std_logic;
    read_error            : out std_logic
    );
end bcm_rod_ram;


architecture bcm_rod_ram_arc of bcm_rod_ram is


  component bcm_rod_dp_ram
    port (
      addra : in  std_logic_vector(8 downto 0);
      addrb : in  std_logic_vector(8 downto 0);
      clka  : in  std_logic;
      clkb  : in  std_logic;
      dina  : in  std_logic_vector(32 downto 0);
      doutb : out std_logic_vector(32 downto 0);
      ena   : in  std_logic;
      enb   : in  std_logic;
      wea   : in  std_logic
      );
  end component;


  component bcm_rod_dp_updown_counter
    port (
      CLK            : in  std_logic;
      CLK_2X         : in  std_logic;
      SCLR           : in  std_logic;
      count_up       : in  std_logic;
      count_down     : in  std_logic;
      busy           : out std_logic;
      data_available : out std_logic;
      write_error    : out std_logic;
      read_error     : out std_logic
      );
  end component;

  signal input_counter   : std_logic_vector(8 downto 0)  := (others => '0');
  signal output_counter  : std_logic_vector(8 downto 0)  := (others => '0');
  signal internal_input  : std_logic_vector(32 downto 0) := (others => '0');
  signal internal_output : std_logic_vector(32 downto 0) := (others => '0');
  signal rd_en           : std_logic                     := '0';
  signal rd_vld          : std_logic                     := '0';

begin


  dp_ram : bcm_rod_dp_ram
    port map (
      addra => input_counter,
      addrb => output_counter,
      clka  => CLK_2X,
      clkb  => CLK ,
      dina  => internal_input,
      doutb => internal_output,
      ena   => '1' ,
      enb   => rd_en,
      wea   => data_input_valid
      );


  fill_counter : bcm_rod_dp_updown_counter
    port map(
      -- clocks and synchronus reset 
      CLK             => CLK,
      CLK_2X         => CLK_2X,
      SCLR            => SCLR,
      -- up/down flags
      count_up       => data_input_valid ,
      count_down     => data_output_next ,
      busy           => busy,
      data_available => data_output_available,
      write_error    => write_error,
      read_error     => read_error
      );

  data_output_vld       <= rd_en                        when rising_edge(CLK);
  internal_input        <= data_input_endoffrag & data_input;
  rd_en                 <= data_output_next;
  data_output           <= internal_output(31 downto 0) when rd_vld = '1' else (others => '0');
  data_output_endoffrag <= internal_output(32)          when rd_vld = '1' else '0';
  rd_vld                <= rd_en                        when rising_edge(CLK);


  ram_input_address : process(CLK_2X, SCLR)
  begin
    if SCLR = '1' then
      input_counter <= (others => '0');
    else
      if CLK_2X'event and CLK_2X = '1' then
        if data_input_valid = '1' then
          input_counter <= (input_counter + "01");
        end if;
      end if;
    end if;
  end process ram_input_address;


  ram_output_address : process(CLK, SCLR)
  begin
    if SCLR = '1' then
      output_counter <= (others => '0');
    else
      if CLK'event and CLK = '1' then
        if data_output_next = '1' then
          output_counter <= (output_counter + "01");
        end if;
      end if;
    end if;
  end process ram_output_address;

end bcm_rod_ram_arc;

---

Author: M.Niegl

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