lcd_commander.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/lcd/lcd_commander.vhd,v $                                                  *
--*  $Revision: 1.8.2.3 $                                                *
--*  $Name: dev $                                                    *
--*  $Author: mniegl $                                                  *
--*  $Date: 2008/11/03 17:57:46 $                                                    *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;





entity lcd_commander is
  port (
    CLOCK     : in    std_logic;
    IN_RS     : in    std_logic;
    IN_DB     : in    std_logic_vector (7 downto 0);
    STROBE    : in    std_logic;
    BUSY      : out   std_logic;
    RS        : out   std_logic;
    RW        : out   std_logic := '0';
    DB        : inout std_logic_vector (7 downto 0);
    DIRECTION : out   std_logic := '0';
    E         : out   std_logic := '1');
end lcd_commander;

architecture lcd_commander_arc of lcd_commander is

  signal INT_ENABLE : std_logic                     := '1';
  signal INT_DATA   : std_logic_vector (7 downto 0);
  signal INT_STATE  : std_logic_vector (2 downto 0) := "000";

begin



  rising_clock : process (CLOCK) is
  begin
    if (CLOCK'event and CLOCK = '1') then
      if INT_STATE = "000" and STROBE = '1' then
        INT_STATE  <= "001";
        INT_ENABLE <= '1';
        BUSY       <= '1';
        INT_DATA   <= IN_DB;
        RS         <= IN_RS;
      elsif INT_STATE = "001" then
        INT_STATE <= "010";
        E         <= '0';
      elsif INT_STATE = "010" then
        INT_STATE  <= "011";
        INT_ENABLE <= '0';
        RS         <= '0';
        RW         <= '1';
        E          <= '1';
      elsif INT_STATE = "011" then
        if DB(7) = '0' then
          INT_STATE <= "100";
        end if;
      elsif INT_STATE = "100" then
        RW        <= '0';
        BUSY      <= '0';
        INT_STATE <= "000";
      end if;
    end if;
  end process;

  DIRECTION <= INT_ENABLE;

  DB <= INT_DATA when INT_ENABLE = '1' else "ZZZZZZZZ";

end lcd_commander_arc;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:04 2008 for BCM-AAA by  1.5.7.1-20081012