mem_interface_top_parameters_0.vhd

Go to the documentation of this file.

--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr/mem_interface_top_parameters_0.vhd,v $
--*  $Revision: 1.4.2.3 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:43 $                              *


--*                                                            *
--**************************************************************
-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  / Vendor: Xilinx
-- \   \   \/ Version: 1.6
--  \   \ Application : MIG
--  /   / Filename: mem_interface_top_parameters_0.vhd
-- /___/   /\ Date Last Modified:  Wed Jun 1 2005
-- \   \  /  \Date Created: Mon May 2 2005
--  \___\/\___\
-- Device: Virtex-4
-- Design Name: DDR1_SDRAM
-------------------------------------------------------------------------------


library ieee;

use ieee.std_logic_1164.all;

library unisim;

use unisim.vcomponents.all;






package mem_interface_top_parameters_0 is

  constant data_width             : integer                       := 32;
  constant data_strobe_width      : integer                       := 4;
  constant data_mask_width        : integer                       := 4;
  constant clk_width              : integer                       := 2;
  constant fifo_16                : integer                       := 2;
  constant ReadEnable             : integer                       := 1;
  constant row_address            : integer                       := 13;
  constant column_address         : integer                       := 9;
  constant bank_address           : integer                       := 2;
  constant memory_width           : integer                       := 8;
  constant DatabitsPerReadClock   : integer                       := 8;
  constant DatabitsPerMask        : integer                       := 8;
  constant no_of_cs               : integer                       := 1;
  constant data_mask              : integer                       := 1;
  constant mask_disable           : integer                       := 0;
  constant RESET                  : integer                       := 0;
  constant dimm                   : integer                       := 0;
  constant comp                   : integer                       := 1;
  constant cke_width              : integer                       := 1;
  constant registered             : integer                       := 0;
  constant unbuffered             : integer                       := 1;
  constant col_ap_width           : integer                       := 11;
  constant tb_enable              : integer                       := 0;
  constant tb_disable             : integer                       := 1;
  constant dcm_enable             : integer                       := 1;
  constant dcm_disable            : integer                       := 0;
  constant low_frequency          : integer                       := 0;
  constant high_frequency         : integer                       := 1;
  constant foundation_ise         : integer                       := 1;
  constant Data8PerReadEnable     : integer                       := 1;
  constant Data4PerReadEnable     : integer                       := 0;
  constant burst_length           : std_logic_vector(2 downto 0)  := "011";
  constant burst_type             : std_logic                     := '0';
  constant cas_latency_value      : std_logic_vector(2 downto 0)  := "011";
  constant Operating_mode         : std_logic_vector(4 downto 0)  := "00000";
  constant load_mode_register     : std_logic_vector(12 downto 0) := "0000000110011";
  constant dll_enable             : std_logic                     := '0';
  constant drive_strengh          : std_logic                     := '0';
  constant ext_load_mode_register : std_logic_vector(12 downto 0) := "0000000000000";
  constant chip_address           : integer                       := 1;
  constant rcd_count_value        : std_logic_vector(2 downto 0)  := "010";
  constant ras_count_value        : std_logic_vector(3 downto 0)  := "0110";
  constant mrd_count_value        : std_logic                     := '0';
  constant rp_count_value         : std_logic_vector(2 downto 0)  := "010";
  constant rfc_count_value        : std_logic_vector(5 downto 0)  := "001011";
  constant twr_count_value        : std_logic_vector(2 downto 0)  := "110";
  constant twtr_count_value       : std_logic_vector(2 downto 0)  := "100";
  constant max_ref_width          : integer                       := 7;
  constant max_ref_cnt            : std_logic_vector(6 downto 0)  := "1001100";
  constant ecc_enable             : std_logic                     := '0';
  constant ecc_disable            : std_logic                     := '1';
  constant ecc_width              : integer                       := 0;
  constant Phy_Mode               : std_logic                     := '1';
  constant trtp_count_value       : std_logic_vector(2 downto 0)  := "011";
  constant odt_enable             : integer                       := 0;
  constant rc_count_value         : std_logic_vector(3 downto 0)  := "1111";  -- active to active same bank = tRC-1
  constant read_enables           : integer                       := 1;
  constant cs_h0                  : std_logic_vector(3 downto 0)  := "0000";
  constant cs_hE                  : std_logic_vector(3 downto 0)  := "1110";
  constant cs_hD                  : std_logic_vector(3 downto 0)  := "1101";
  constant cs_hB                  : std_logic_vector(3 downto 0)  := "1011";
  constant cs_h7                  : std_logic_vector(3 downto 0)  := "0111";
  constant cs_hF                  : std_logic_vector(3 downto 0)  := "1111";
  constant add_const1             : std_logic_vector(15 downto 0) := X"0400";
  constant add_const2             : std_logic_vector(15 downto 0) := X"0100";
  constant add_const3             : std_logic_vector(15 downto 0) := X"0000";
  constant add_const4             : std_logic_vector(15 downto 0) := X"FBFF";
  constant add_const5             : std_logic_vector(15 downto 0) := X"FEFF";

end mem_interface_top_parameters_0;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:04 2008 for BCM-AAA by  1.5.7.1-20081012