bcm_rod_dp_updown_counter.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/rod/bcm_rod_dp_updown_counter.vhd,v $                                                  *
--*  $Revision: 1.13.2.4 $                                         *
--*  $Name: dev $                                              *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:48 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;







entity bcm_rod_dp_updown_counter is
  port (
    -- clocks and synchronus reset
    CLK            : in  std_logic;
    CLK_2X         : in  std_logic;
    SCLR           : in  std_logic;
    -- up/down flags
    count_up       : in  std_logic;
    count_down     : in  std_logic;
    busy           : out std_logic;
    data_available : out std_logic;
    write_error    : out std_logic;
    read_error     : out std_logic
    );
end bcm_rod_dp_updown_counter;


architecture bcm_rod_dp_updown_counter_arc of bcm_rod_dp_updown_counter is

  signal dp_ram_updown_counter : std_logic_vector(8 downto 0) := (others => '0');

begin







  ram_fill_counter : process(CLK_2X)
  begin
    if (CLK_2X'event and CLK_2X = '1') then
      if (SCLR = '1') then              -- synchronous clear (reset)
        dp_ram_updown_counter <= (others => '0');
        busy                  <= '0';
        data_available        <= '0';
        write_error           <= '0';
        read_error            <= '0';
      else
        if ((count_up = '1' and count_down = '0') or (count_up = '1' and count_down = '1' and CLK = '0')) then  -- only counting up
          if (dp_ram_updown_counter = "111111111") then  -- counter full - data could not be stored in RAM
            dp_ram_updown_counter <= dp_ram_updown_counter;
            write_error           <= '1';
            busy                  <= '1';
          else              -- counter not full - data could be stored in RAM
            dp_ram_updown_counter <= (dp_ram_updown_counter + "01");
            write_error           <= '0';
            if (dp_ram_updown_counter >= "111111101") then
              busy <= '1';
            else
              busy <= '0';
            end if;
          end if;
          data_available <= '1';
          read_error     <= '0';
        elsif (count_up = '0' and count_down = '1' and CLK = '1') then  -- only counting down
          if (dp_ram_updown_counter = "000000000") then  -- counter full - data could not be stored in RAM
            dp_ram_updown_counter <= dp_ram_updown_counter;
            read_error            <= '1';
            data_available        <= '0';
          else              -- counter not full - data could be stored in RAM
            dp_ram_updown_counter     <= (dp_ram_updown_counter - "01"); 
            read_error                <= '0';
            if (dp_ram_updown_counter <= "000000001") then
              data_available <= '0';
            else
              data_available <= '1';
            end if;
          end if;
          write_error <= '0';
          busy        <= '0';
        else                -- counting up and down or no counting at all
          dp_ram_updown_counter <= dp_ram_updown_counter;
          if (count_down = '0') then
            read_error <= '0';
          end if;
          if (dp_ram_updown_counter = "000000000") then
            data_available <= '0';
          else
            data_available <= '1';
          end if;
          if (dp_ram_updown_counter >= "111111110") then
            busy <= '1';
          else
            busy <= '0';
          end if;
          write_error <= '0';
        end if;
      end if;
    end if;
  end process;

end bcm_rod_dp_updown_counter_arc;

---

Author: M.Niegl

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