delay_adj.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/rio/delay_adj.vhd,v $*
--*  $Revision: 1.8.2.4 $                                          *
--*  $Name: dev $                                              *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:47 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;




entity delay_adj is
  port (
    CLK        : in  std_logic;
    A          : in  std_logic_vector (31 downto 0);
    B          : in  std_logic_vector (31 downto 0);
    X          : out std_logic_vector (31 downto 0);
    Y          : out std_logic_vector (31 downto 0);
    ADJ_TIME_1 : in  integer range 0 to 32;
    ADJ_TIME_2 : in  integer range 0 to 32
    );
end delay_adj;




architecture delay_adj_arc of delay_adj is

  signal a_i : std_logic_vector (63 downto 0) := (others => '0');
  signal b_i : std_logic_vector (63 downto 0) := (others => '0');

begin


  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      a_i <= A & a_i(63 downto 32);
      b_i <= B & b_i(63 downto 32);
      X   <= a_i(63-ADJ_TIME_1 downto 32-ADJ_TIME_1);
      Y   <= b_i(63-ADJ_TIME_2 downto 32-ADJ_TIME_2);
    end if;
  end process;
  
end delay_adj_arc;

---

Author: M.Niegl

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