BCM-AAA: ctp_logic.vhd Source File

00001 --**************************************************************
00002 --*                                                            *
00003 --*     The source code for the ATLAS BCM "AAA" FPGA is made   *
00004 --*     available via the GNU General Public License (GPL)     *
00005 --*     unless otherwise stated below.                         *
00006 --*                                                            *
00007 --*     In case of problems/questions/bug reports etc. please  *
00008 --*     contact michael.niegl@cern.ch                          *
00009 --*                                                            *
00010 --**************************************************************
00011 
00012 --**************************************************************
00013 --*                                                            *
00014 --*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/div/ctp_logic.vhd,v $
00015 --*  $Revision: 1.10.2.13 $                                          *
00016 --*  $Name: dev $                                                 *
00017 --*  $Author: mniegl $                                         *
00018 --*  $Date: 2008/11/03 17:57:45 $                              *
00019 
00020 
00021 
00022 --*                                                            *
00023 --**************************************************************
00024 
00025 library ieee;
00026 
00027 use ieee.std_logic_1164.all;
00028 
00029 use ieee.std_logic_arith.all;
00030 
00031 use ieee.std_logic_unsigned.all;
00032 
00033 use ieee.numeric_std.all;
00034 
00035 library unisim;
00036 
00037 use unisim.vcomponents.all;
00038 library work;
00039 use work.daq_header.all;
00040 use work.main_components.all;
00041 use work.build_parameters.all;
00042 
00043 
00044 
00045 
00046 
00047 
00048 
00049 
00050 
00051 
00052 
00053 entity ctp_logic is
00054   port (
00055     CLK              : in  std_logic;
00056     UPPER_BOUND_A    : in  std_logic_vector(5 downto 0) := "101110";
00057     LOWER_BOUND_A    : in  std_logic_vector(5 downto 0) := "010000";
00058     UPPER_BOUND_C    : in  std_logic_vector(5 downto 0) := "101110";
00059     LOWER_BOUND_C    : in  std_logic_vector(5 downto 0) := "010000";
00060     UPPER_BOUND_A1   : in  std_logic_vector(5 downto 0) := "101110";
00061     LOWER_BOUND_A1   : in  std_logic_vector(5 downto 0) := "010000";
00062     UPPER_BOUND_C1   : in  std_logic_vector(5 downto 0) := "101110";
00063     LOWER_BOUND_C1   : in  std_logic_vector(5 downto 0) := "010000";
00064     UPPER_BOUND_AW   : in  std_logic_vector(5 downto 0) := "111111";
00065     LOWER_BOUND_AW   : in  std_logic_vector(5 downto 0) := "000001";
00066     UPPER_BOUND_CW   : in  std_logic_vector(5 downto 0) := "111111";
00067     LOWER_BOUND_CW   : in  std_logic_vector(5 downto 0) := "000001";
00068     IRENA1           : in  std_logic_vector (7 downto 0);
00069     EWA1             : in  std_logic_vector (7 downto 0);
00070     HEINZ1           : in  std_logic_vector (7 downto 0);
00071     ANDREJ1          : in  std_logic_vector (7 downto 0);
00072     MARKO1           : in  std_logic_vector (7 downto 0);
00073     WILLIAM1         : in  std_logic_vector (7 downto 0);
00074     HARRIS1          : in  std_logic_vector (7 downto 0);
00075     HELMUT1          : in  std_logic_vector (7 downto 0);
00076     IRENA2           : in  std_logic_vector (7 downto 0);
00077     EWA2             : in  std_logic_vector (7 downto 0);
00078     HEINZ2           : in  std_logic_vector (7 downto 0);
00079     ANDREJ2          : in  std_logic_vector (7 downto 0);
00080     MARKO2           : in  std_logic_vector (7 downto 0);
00081     WILLIAM2         : in  std_logic_vector (7 downto 0);
00082     HARRIS2          : in  std_logic_vector (7 downto 0);
00083     HELMUT2          : in  std_logic_vector (7 downto 0);
00084     S_IRENA1         : in  std_logic;
00085     S_EWA1           : in  std_logic;
00086     S_HEINZ1         : in  std_logic;
00087     S_ANDREJ1        : in  std_logic;
00088     S_MARKO1         : in  std_logic;
00089     S_WILLIAM1       : in  std_logic;
00090     S_HARRIS1        : in  std_logic;
00091     S_HELMUT1        : in  std_logic;
00092     S_IRENA2         : in  std_logic;
00093     S_EWA2           : in  std_logic;
00094     S_HEINZ2         : in  std_logic;
00095     S_ANDREJ2        : in  std_logic;
00096     S_MARKO2         : in  std_logic;
00097     S_WILLIAM2       : in  std_logic;
00098     S_HARRIS2        : in  std_logic;
00099     S_HELMUT2        : in  std_logic;
00100     OTHER_IRENA1     : in  std_logic_vector(7 downto 0) := "00000000";
00101     OTHER_EWA1       : in  std_logic_vector(7 downto 0) := "00000000";
00102     OTHER_HEINZ1     : in  std_logic_vector(7 downto 0) := "00000000";
00103     OTHER_ANDREJ1    : in  std_logic_vector(7 downto 0) := "00000000";
00104     OTHER_MARKO1     : in  std_logic_vector(7 downto 0) := "00000000";
00105     OTHER_WILLIAM1   : in  std_logic_vector(7 downto 0) := "00000000";
00106     OTHER_HARRIS1    : in  std_logic_vector(7 downto 0) := "00000000";
00107     OTHER_HELMUT1    : in  std_logic_vector(7 downto 0) := "00000000";
00108     OTHER_IRENA2     : in  std_logic_vector(7 downto 0) := "00000000";
00109     OTHER_EWA2       : in  std_logic_vector(7 downto 0) := "00000000";
00110     OTHER_HEINZ2     : in  std_logic_vector(7 downto 0) := "00000000";
00111     OTHER_ANDREJ2    : in  std_logic_vector(7 downto 0) := "00000000";
00112     OTHER_MARKO2     : in  std_logic_vector(7 downto 0) := "00000000";
00113     OTHER_WILLIAM2   : in  std_logic_vector(7 downto 0) := "00000000";
00114     OTHER_HARRIS2    : in  std_logic_vector(7 downto 0) := "00000000";
00115     OTHER_HELMUT2    : in  std_logic_vector(7 downto 0) := "00000000";
00116     OTHER_S_IRENA1   : in  std_logic                    := '0';
00117     OTHER_S_EWA1     : in  std_logic                    := '0';
00118     OTHER_S_HEINZ1   : in  std_logic                    := '0';
00119     OTHER_S_ANDREJ1  : in  std_logic                    := '0';
00120     OTHER_S_MARKO1   : in  std_logic                    := '0';
00121     OTHER_S_WILLIAM1 : in  std_logic                    := '0';
00122     OTHER_S_HARRIS1  : in  std_logic                    := '0';
00123     OTHER_S_HELMUT1  : in  std_logic                    := '0';
00124     OTHER_S_IRENA2   : in  std_logic                    := '0';
00125     OTHER_S_EWA2     : in  std_logic                    := '0';
00126     OTHER_S_HEINZ2   : in  std_logic                    := '0';
00127     OTHER_S_ANDREJ2  : in  std_logic                    := '0';
00128     OTHER_S_MARKO2   : in  std_logic                    := '0';
00129     OTHER_S_WILLIAM2 : in  std_logic                    := '0';
00130     OTHER_S_HARRIS2  : in  std_logic                    := '0';
00131     OTHER_S_HELMUT2  : in  std_logic                    := '0';
00132     CTP_OUT          : out std_logic_vector(9 downto 1)
00133     );
00134 
00135 end ctp_logic;
00136 
00137 
00138 
00139 
00140 
00141 
00142 
00143 
00144 
00145 
00146 architecture ctp_logic_arc of ctp_logic is
00147 
00148 --*************************** Signal Declarations *****************************
00149   alias clk5x is CLK;
00150 
00151   signal BCM_AtoC          : std_logic                    := '0';
00152   signal BCM_CtoA          : std_logic                    := '0';
00153   signal BCM_wide          : std_logic                    := '0';
00154   signal BCM_A             : std_logic_vector(1 downto 0) := "00";
00155   signal BCM_C             : std_logic_vector(1 downto 0) := "00";
00156   signal BCM_AttHitA       : std_logic                    := '0';
00157   signal BCM_AttHitC       : std_logic                    := '0';
00158   signal atoc_a            : std_logic                    := '0';
00159   signal atoc_c            : std_logic                    := '0';
00160   signal ctoa_a            : std_logic                    := '0';
00161   signal ctoa_c            : std_logic                    := '0';
00162   signal wide_a            : std_logic                    := '0';
00163   signal wide_c            : std_logic                    := '0';
00164   signal hit_atta          : std_logic                    := '0';
00165   signal hit_attc          : std_logic                    := '0';
00166   signal mult_a            : std_logic_vector(1 downto 0) := "00";
00167   signal mult_c            : std_logic_vector(1 downto 0) := "00";
00168   signal mult_a1           : std_logic_vector(1 downto 0) := "00";
00169   signal mult_c1           : std_logic_vector(1 downto 0) := "00";
00170   signal mult_a2           : std_logic_vector(1 downto 0) := "00";
00171   signal mult_c2           : std_logic_vector(1 downto 0) := "00";
00172   signal hit_irena         : std_logic_vector(1 downto 0) := "00";
00173   signal hit_ewa           : std_logic_vector(1 downto 0) := "00";
00174   signal hit_heinz         : std_logic_vector(1 downto 0) := "00";
00175   signal hit_andrej        : std_logic_vector(1 downto 0) := "00";
00176   signal hit_marko         : std_logic_vector(1 downto 0) := "00";
00177   signal hit_william       : std_logic_vector(1 downto 0) := "00";
00178   signal hit_harris        : std_logic_vector(1 downto 0) := "00";
00179   signal hit_helmut        : std_logic_vector(1 downto 0) := "00";
00180   signal irena1_bc         : std_logic_vector(5 downto 0) := (others => '0');
00181   signal ewa1_bc           : std_logic_vector(5 downto 0) := (others => '0');
00182   signal heinz1_bc         : std_logic_vector(5 downto 0) := (others => '0');
00183   signal andrej1_bc        : std_logic_vector(5 downto 0) := (others => '0');
00184   signal marko1_bc         : std_logic_vector(5 downto 0) := (others => '0');
00185   signal william1_bc       : std_logic_vector(5 downto 0) := (others => '0');
00186   signal harris1_bc        : std_logic_vector(5 downto 0) := (others => '0');
00187   signal helmut1_bc        : std_logic_vector(5 downto 0) := (others => '0');
00188   signal irena2_bc         : std_logic_vector(5 downto 0) := (others => '0');
00189   signal ewa2_bc           : std_logic_vector(5 downto 0) := (others => '0');
00190   signal heinz2_bc         : std_logic_vector(5 downto 0) := (others => '0');
00191   signal andrej2_bc        : std_logic_vector(5 downto 0) := (others => '0');
00192   signal marko2_bc         : std_logic_vector(5 downto 0) := (others => '0');
00193   signal william2_bc       : std_logic_vector(5 downto 0) := (others => '0');
00194   signal harris2_bc        : std_logic_vector(5 downto 0) := (others => '0');
00195   signal helmut2_bc        : std_logic_vector(5 downto 0) := (others => '0');
00196   signal hit_irena1        : std_logic                    := '0';
00197   signal hit_ewa1          : std_logic                    := '0';
00198   signal hit_heinz1        : std_logic                    := '0';
00199   signal hit_andrej1       : std_logic                    := '0';
00200   signal hit_marko1        : std_logic                    := '0';
00201   signal hit_william1      : std_logic                    := '0';
00202   signal hit_harris1       : std_logic                    := '0';
00203   signal hit_helmut1       : std_logic                    := '0';
00204   signal hit_irena2        : std_logic                    := '0';
00205   signal hit_ewa2          : std_logic                    := '0';
00206   signal hit_heinz2        : std_logic                    := '0';
00207   signal hit_andrej2       : std_logic                    := '0';
00208   signal hit_marko2        : std_logic                    := '0';
00209   signal hit_william2      : std_logic                    := '0';
00210   signal hit_harris2       : std_logic                    := '0';
00211   signal hit_helmut2       : std_logic                    := '0';
00212   signal hit_irena11       : std_logic                    := '0';
00213   signal hit_ewa11         : std_logic                    := '0';
00214   signal hit_heinz11       : std_logic                    := '0';
00215   signal hit_andrej11      : std_logic                    := '0';
00216   signal hit_marko11       : std_logic                    := '0';
00217   signal hit_william11     : std_logic                    := '0';
00218   signal hit_harris11      : std_logic                    := '0';
00219   signal hit_helmut11      : std_logic                    := '0';
00220   signal hit_irena21       : std_logic                    := '0';
00221   signal hit_ewa21         : std_logic                    := '0';
00222   signal hit_heinz21       : std_logic                    := '0';
00223   signal hit_andrej21      : std_logic                    := '0';
00224   signal hit_marko21       : std_logic                    := '0';
00225   signal hit_william21     : std_logic                    := '0';
00226   signal hit_harris21      : std_logic                    := '0';
00227   signal hit_helmut21      : std_logic                    := '0';
00228   signal hit_irena1w       : std_logic                    := '0';
00229   signal hit_ewa1w         : std_logic                    := '0';
00230   signal hit_heinz1w       : std_logic                    := '0';
00231   signal hit_andrej1w      : std_logic                    := '0';
00232   signal hit_marko1w       : std_logic                    := '0';
00233   signal hit_william1w     : std_logic                    := '0';
00234   signal hit_harris1w      : std_logic                    := '0';
00235   signal hit_helmut1w      : std_logic                    := '0';
00236   signal hit_irena2w       : std_logic                    := '0';
00237   signal hit_ewa2w         : std_logic                    := '0';
00238   signal hit_heinz2w       : std_logic                    := '0';
00239   signal hit_andrej2w      : std_logic                    := '0';
00240   signal hit_marko2w       : std_logic                    := '0';
00241   signal hit_william2w     : std_logic                    := '0';
00242   signal hit_harris2w      : std_logic                    := '0';
00243   signal hit_helmut2w      : std_logic                    := '0';
00244   signal oth_hit_irena     : std_logic_vector(1 downto 0) := "00";
00245   signal oth_hit_ewa       : std_logic_vector(1 downto 0) := "00";
00246   signal oth_hit_heinz     : std_logic_vector(1 downto 0) := "00";
00247   signal oth_hit_andrej    : std_logic_vector(1 downto 0) := "00";
00248   signal oth_hit_marko     : std_logic_vector(1 downto 0) := "00";
00249   signal oth_hit_william   : std_logic_vector(1 downto 0) := "00";
00250   signal oth_hit_harris    : std_logic_vector(1 downto 0) := "00";
00251   signal oth_hit_helmut    : std_logic_vector(1 downto 0) := "00";
00252   signal oth_irena1_bc     : std_logic_vector(5 downto 0) := (others => '0');
00253   signal oth_ewa1_bc       : std_logic_vector(5 downto 0) := (others => '0');
00254   signal oth_heinz1_bc     : std_logic_vector(5 downto 0) := (others => '0');
00255   signal oth_andrej1_bc    : std_logic_vector(5 downto 0) := (others => '0');
00256   signal oth_marko1_bc     : std_logic_vector(5 downto 0) := (others => '0');
00257   signal oth_william1_bc   : std_logic_vector(5 downto 0) := (others => '0');
00258   signal oth_harris1_bc    : std_logic_vector(5 downto 0) := (others => '0');
00259   signal oth_helmut1_bc    : std_logic_vector(5 downto 0) := (others => '0');
00260   signal oth_irena2_bc     : std_logic_vector(5 downto 0) := (others => '0');
00261   signal oth_ewa2_bc       : std_logic_vector(5 downto 0) := (others => '0');
00262   signal oth_heinz2_bc     : std_logic_vector(5 downto 0) := (others => '0');
00263   signal oth_andrej2_bc    : std_logic_vector(5 downto 0) := (others => '0');
00264   signal oth_marko2_bc     : std_logic_vector(5 downto 0) := (others => '0');
00265   signal oth_william2_bc   : std_logic_vector(5 downto 0) := (others => '0');
00266   signal oth_harris2_bc    : std_logic_vector(5 downto 0) := (others => '0');
00267   signal oth_helmut2_bc    : std_logic_vector(5 downto 0) := (others => '0');
00268   signal oth_hit_irena1    : std_logic                    := '0';
00269   signal oth_hit_ewa1      : std_logic                    := '0';
00270   signal oth_hit_heinz1    : std_logic                    := '0';
00271   signal oth_hit_andrej1   : std_logic                    := '0';
00272   signal oth_hit_marko1    : std_logic                    := '0';
00273   signal oth_hit_william1  : std_logic                    := '0';
00274   signal oth_hit_harris1   : std_logic                    := '0';
00275   signal oth_hit_helmut1   : std_logic                    := '0';
00276   signal oth_hit_irena2    : std_logic                    := '0';
00277   signal oth_hit_ewa2      : std_logic                    := '0';
00278   signal oth_hit_heinz2    : std_logic                    := '0';
00279   signal oth_hit_andrej2   : std_logic                    := '0';
00280   signal oth_hit_marko2    : std_logic                    := '0';
00281   signal oth_hit_william2  : std_logic                    := '0';
00282   signal oth_hit_harris2   : std_logic                    := '0';
00283   signal oth_hit_helmut2   : std_logic                    := '0';
00284   signal oth_hit_irena11   : std_logic                    := '0';
00285   signal oth_hit_ewa11     : std_logic                    := '0';
00286   signal oth_hit_heinz11   : std_logic                    := '0';
00287   signal oth_hit_andrej11  : std_logic                    := '0';
00288   signal oth_hit_marko11   : std_logic                    := '0';
00289   signal oth_hit_william11 : std_logic                    := '0';
00290   signal oth_hit_harris11  : std_logic                    := '0';
00291   signal oth_hit_helmut11  : std_logic                    := '0';
00292   signal oth_hit_irena21   : std_logic                    := '0';
00293   signal oth_hit_ewa21     : std_logic                    := '0';
00294   signal oth_hit_heinz21   : std_logic                    := '0';
00295   signal oth_hit_andrej21  : std_logic                    := '0';
00296   signal oth_hit_marko21   : std_logic                    := '0';
00297   signal oth_hit_william21 : std_logic                    := '0';
00298   signal oth_hit_harris21  : std_logic                    := '0';
00299   signal oth_hit_helmut21  : std_logic                    := '0';
00300   signal oth_hit_irena1w   : std_logic                    := '0';
00301   signal oth_hit_ewa1w     : std_logic                    := '0';
00302   signal oth_hit_heinz1w   : std_logic                    := '0';
00303   signal oth_hit_andrej1w  : std_logic                    := '0';
00304   signal oth_hit_marko1w   : std_logic                    := '0';
00305   signal oth_hit_william1w : std_logic                    := '0';
00306   signal oth_hit_harris1w  : std_logic                    := '0';
00307   signal oth_hit_helmut1w  : std_logic                    := '0';
00308   signal oth_hit_irena2w   : std_logic                    := '0';
00309   signal oth_hit_ewa2w     : std_logic                    := '0';
00310   signal oth_hit_heinz2w   : std_logic                    := '0';
00311   signal oth_hit_andrej2w  : std_logic                    := '0';
00312   signal oth_hit_marko2w   : std_logic                    := '0';
00313   signal oth_hit_william2w : std_logic                    := '0';
00314   signal oth_hit_harris2w  : std_logic                    := '0';
00315   signal oth_hit_helmut2w  : std_logic                    := '0';
00316 
00317 --************************** Component Declarations ***************************
00318 
00319 
00320   component timewindow
00321     port(
00322       CLK     : in  std_logic;
00323       UPPER   :     std_logic_vector(5 downto 0) := "101110";
00324       LOWER   :     std_logic_vector(5 downto 0) := "010000";
00325       VAL_IN  : in  std_logic_vector(5 downto 0);
00326       VAL_OUT : out std_logic_vector(5 downto 0);
00327       IN_TIME : out std_logic
00328       );
00329   end component;
00330 
00331 --*************************************************************************
00332 --*                               main code
00333 --*************************************************************************
00334 begin
00335 
00336 -- input assignments
00337   irena1_bc   <= IRENA1(5 downto 0)   when S_IRENA1 = '1'   else (others => '0');
00338   ewa1_bc     <= EWA1(5 downto 0)     when S_EWA1 = '1'     else (others => '0');
00339   heinz1_bc   <= HEINZ1(5 downto 0)   when S_HEINZ1 = '1'   else (others => '0');
00340   andrej1_bc  <= ANDREJ1(5 downto 0)  when S_ANDREJ1 = '1'  else (others => '0');
00341   marko1_bc   <= MARKO1(5 downto 0)   when S_MARKO1 = '1'   else (others => '0');
00342   william1_bc <= WILLIAM1(5 downto 0) when S_WILLIAM1 = '1' else (others => '0');
00343   harris1_bc  <= HARRIS1(5 downto 0)  when S_HARRIS1 = '1'  else (others => '0');
00344   helmut1_bc  <= HELMUT1(5 downto 0)  when S_HELMUT1 = '1'  else (others => '0');
00345   irena2_bc   <= IRENA2(5 downto 0)   when S_IRENA2 = '1'   else (others => '0');
00346   ewa2_bc     <= EWA2(5 downto 0)     when S_EWA2 = '1'     else (others => '0');
00347   heinz2_bc   <= HEINZ2(5 downto 0)   when S_HEINZ2 = '1'   else (others => '0');
00348   andrej2_bc  <= ANDREJ2(5 downto 0)  when S_ANDREJ2 = '1'  else (others => '0');
00349   marko2_bc   <= MARKO2(5 downto 0)   when S_MARKO2 = '1'   else (others => '0');
00350   william2_bc <= WILLIAM2(5 downto 0) when S_WILLIAM2 = '1' else (others => '0');
00351   harris2_bc  <= HARRIS2(5 downto 0)  when S_HARRIS2 = '1'  else (others => '0');
00352   helmut2_bc  <= HELMUT2(5 downto 0)  when S_HELMUT2 = '1'  else (others => '0');
00353 
00354   hit_irena   <= '0' & (S_IRENA1 or S_IRENA2);
00355   hit_ewa     <= '0' & (S_EWA1 or S_EWA2);
00356   hit_andrej  <= '0' & (S_ANDREJ1 or S_ANDREJ2);
00357   hit_heinz   <= '0' & (S_HEINZ1 or S_HEINZ2);
00358   hit_marko   <= '0' & (S_MARKO1 or S_MARKO2);
00359   hit_william <= '0' & (S_WILLIAM1 or S_WILLIAM2);
00360   hit_harris  <= '0' & (S_HARRIS1 or S_HARRIS2);
00361   hit_helmut  <= '0' & (S_HELMUT1 or S_HELMUT2);
00362 
00363   oth_irena1_bc   <= OTHER_IRENA1(5 downto 0)   when OTHER_S_IRENA1 = '1'   else (others => '0');
00364   oth_ewa1_bc     <= OTHER_EWA1(5 downto 0)     when OTHER_S_EWA1 = '1'     else (others => '0');
00365   oth_heinz1_bc   <= OTHER_HEINZ1(5 downto 0)   when OTHER_S_HEINZ1 = '1'   else (others => '0');
00366   oth_andrej1_bc  <= OTHER_ANDREJ1(5 downto 0)  when OTHER_S_ANDREJ1 = '1'  else (others => '0');
00367   oth_marko1_bc   <= OTHER_MARKO1(5 downto 0)   when OTHER_S_MARKO1 = '1'   else (others => '0');
00368   oth_william1_bc <= OTHER_WILLIAM1(5 downto 0) when OTHER_S_WILLIAM1 = '1' else (others => '0');
00369   oth_harris1_bc  <= OTHER_HARRIS1(5 downto 0)  when OTHER_S_HARRIS1 = '1'  else (others => '0');
00370   oth_helmut1_bc  <= OTHER_HELMUT1(5 downto 0)  when OTHER_S_HELMUT1 = '1'  else (others => '0');
00371   oth_irena2_bc   <= OTHER_IRENA2(5 downto 0)   when OTHER_S_IRENA2 = '1'   else (others => '0');
00372   oth_ewa2_bc     <= OTHER_EWA2(5 downto 0)     when OTHER_S_EWA2 = '1'     else (others => '0');
00373   oth_heinz2_bc   <= OTHER_HEINZ2(5 downto 0)   when OTHER_S_HEINZ2 = '1'   else (others => '0');
00374   oth_andrej2_bc  <= OTHER_ANDREJ2(5 downto 0)  when OTHER_S_ANDREJ2 = '1'  else (others => '0');
00375   oth_marko2_bc   <= OTHER_MARKO2(5 downto 0)   when OTHER_S_MARKO2 = '1'   else (others => '0');
00376   oth_william2_bc <= OTHER_WILLIAM2(5 downto 0) when OTHER_S_WILLIAM2 = '1' else (others => '0');
00377   oth_harris2_bc  <= OTHER_HARRIS2(5 downto 0)  when OTHER_S_HARRIS2 = '1'  else (others => '0');
00378   oth_helmut2_bc  <= OTHER_HELMUT2(5 downto 0)  when OTHER_S_HELMUT2 = '1'  else (others => '0');
00379 
00380   oth_hit_irena   <= '0' & (OTHER_S_IRENA1 or OTHER_S_IRENA2);
00381   oth_hit_ewa     <= '0' & (OTHER_S_EWA1 or OTHER_S_EWA2);
00382   oth_hit_andrej  <= '0' & (OTHER_S_ANDREJ1 or OTHER_S_ANDREJ2);
00383   oth_hit_heinz   <= '0' & (OTHER_S_HEINZ1 or OTHER_S_HEINZ2);
00384   oth_hit_marko   <= '0' & (OTHER_S_MARKO1 or OTHER_S_MARKO2);
00385   oth_hit_william <= '0' & (OTHER_S_WILLIAM1 or OTHER_S_WILLIAM2);
00386   oth_hit_harris  <= '0' & (OTHER_S_HARRIS1 or OTHER_S_HARRIS2);
00387   oth_hit_helmut  <= '0' & (OTHER_S_HELMUT1 or OTHER_S_HELMUT2);
00388 
00389   -----------------------------------------------------------------------------
00390   -- A to C, local ROD
00391   -----------------------------------------------------------------------------
00392   Irena_1 : timewindow
00393     port map
00394     (
00395       CLK     => clk5x,
00396       UPPER   => UPPER_BOUND_A,
00397       LOWER   => LOWER_BOUND_A,
00398       VAL_IN  => irena1_bc,
00399       VAL_OUT => open,
00400       IN_TIME => hit_irena1
00401       );
00402   Irena_2 : timewindow
00403     port map
00404     (
00405       CLK     => clk5x,
00406       UPPER   => UPPER_BOUND_A,
00407       LOWER   => LOWER_BOUND_A,
00408       VAL_IN  => irena2_bc,
00409       VAL_OUT => open,
00410       IN_TIME => hit_irena2
00411       );
00412 
00413   ewa_1 : timewindow
00414     port map
00415     (
00416       CLK     => clk5x,
00417       UPPER   => UPPER_BOUND_A,
00418       LOWER   => LOWER_BOUND_A,
00419       VAL_IN  => ewa1_bc,
00420       VAL_OUT => open,
00421       IN_TIME => hit_ewa1
00422       );
00423   ewa_2 : timewindow
00424     port map
00425     (
00426       CLK     => clk5x,
00427       UPPER   => UPPER_BOUND_A,
00428       LOWER   => LOWER_BOUND_A,
00429       VAL_IN  => ewa2_bc,
00430       VAL_OUT => open,
00431       IN_TIME => hit_ewa2
00432       );
00433 
00434   heinz_1 : timewindow
00435     port map
00436     (
00437       CLK     => clk5x,
00438       UPPER   => UPPER_BOUND_A,
00439       LOWER   => LOWER_BOUND_A,
00440       VAL_IN  => heinz1_bc,
00441       VAL_OUT => open,
00442       IN_TIME => hit_heinz1
00443       );
00444   heinz_2 : timewindow
00445     port map
00446     (
00447       CLK     => clk5x,
00448       UPPER   => UPPER_BOUND_A,
00449       LOWER   => LOWER_BOUND_A,
00450       VAL_IN  => heinz2_bc,
00451       VAL_OUT => open,
00452       IN_TIME => hit_heinz2
00453       );
00454 
00455   andrej_1 : timewindow
00456     port map
00457     (
00458       CLK     => clk5x,
00459       UPPER   => UPPER_BOUND_A,
00460       LOWER   => LOWER_BOUND_A,
00461       VAL_IN  => andrej1_bc ,
00462       VAL_OUT => open,
00463       IN_TIME => hit_andrej1 
00464       );
00465   andrej_2 : timewindow
00466     port map
00467     (
00468       CLK     => clk5x,
00469       UPPER   => UPPER_BOUND_A,
00470       LOWER   => LOWER_BOUND_A,
00471       VAL_IN  => andrej2_bc ,
00472       VAL_OUT => open,
00473       IN_TIME => hit_andrej2 
00474       );
00475 
00476   marko_1 : timewindow
00477     port map
00478     (
00479       CLK     => clk5x,
00480       UPPER   => UPPER_BOUND_C,
00481       LOWER   => LOWER_BOUND_C,
00482       VAL_IN  => marko1_bc,
00483       VAL_OUT => open,
00484       IN_TIME => hit_marko1
00485       );
00486   marko_2 : timewindow
00487     port map
00488     (
00489       CLK     => clk5x,
00490       UPPER   => UPPER_BOUND_C,
00491       LOWER   => LOWER_BOUND_C,
00492       VAL_IN  => marko2_bc,
00493       VAL_OUT => open,
00494       IN_TIME => hit_marko2
00495       );
00496 
00497   william_1 : timewindow
00498     port map
00499     (
00500       CLK     => clk5x,
00501       UPPER   => UPPER_BOUND_C,
00502       LOWER   => LOWER_BOUND_C,
00503       VAL_IN  => william1_bc ,
00504       VAL_OUT => open,
00505       IN_TIME => hit_william1
00506       );
00507   william_2 : timewindow
00508     port map
00509     (
00510       CLK     => clk5x,
00511       UPPER   => UPPER_BOUND_C,
00512       LOWER   => LOWER_BOUND_C,
00513       VAL_IN  => william2_bc ,
00514       VAL_OUT => open,
00515       IN_TIME => hit_william2
00516       );
00517 
00518   harris_1 : timewindow
00519     port map
00520     (
00521       CLK     => clk5x,
00522       UPPER   => UPPER_BOUND_C,
00523       LOWER   => LOWER_BOUND_C,
00524       VAL_IN  => harris1_bc ,
00525       VAL_OUT => open,
00526       IN_TIME => hit_harris1 
00527       );
00528   harris_2 : timewindow
00529     port map
00530     (
00531       CLK     => clk5x,
00532       UPPER   => UPPER_BOUND_C,
00533       LOWER   => LOWER_BOUND_C,
00534       VAL_IN  => harris2_bc ,
00535       VAL_OUT => open,
00536       IN_TIME => hit_harris2 
00537       );
00538 
00539   helmut_1 : timewindow
00540     port map
00541     (
00542       CLK     => clk5x,
00543       UPPER   => UPPER_BOUND_C,
00544       LOWER   => LOWER_BOUND_C,
00545       VAL_IN  => helmut1_bc ,
00546       VAL_OUT => open,
00547       IN_TIME => hit_helmut1 
00548       );
00549   helmut_2 : timewindow
00550     port map
00551     (
00552       CLK     => clk5x,
00553       UPPER   => UPPER_BOUND_C,
00554       LOWER   => LOWER_BOUND_C,
00555       VAL_IN  => helmut2_bc ,
00556       VAL_OUT => open,
00557       IN_TIME => hit_helmut2 
00558       );
00559 
00560   -----------------------------------------------------------------------------
00561   -- A to C, remote ROD
00562   -----------------------------------------------------------------------------
00563   oth_Irena_1 : timewindow
00564     port map
00565     (
00566       CLK     => clk5x,
00567       UPPER   => UPPER_BOUND_A,
00568       LOWER   => LOWER_BOUND_A,
00569       VAL_IN  => oth_irena1_bc,
00570       VAL_OUT => open,
00571       IN_TIME => oth_hit_irena1
00572       );
00573   oth_Irena_2 : timewindow
00574     port map
00575     (
00576       CLK     => clk5x,
00577       UPPER   => UPPER_BOUND_A,
00578       LOWER   => LOWER_BOUND_A,
00579       VAL_IN  => oth_irena2_bc,
00580       VAL_OUT => open,
00581       IN_TIME => oth_hit_irena2
00582       );
00583 
00584   oth_ewa_1 : timewindow
00585     port map
00586     (
00587       CLK     => clk5x,
00588       UPPER   => UPPER_BOUND_A,
00589       LOWER   => LOWER_BOUND_A,
00590       VAL_IN  => oth_ewa1_bc ,
00591       VAL_OUT => open,
00592       IN_TIME => oth_hit_ewa1
00593       );
00594   oth_ewa_2 : timewindow
00595     port map
00596     (
00597       CLK     => clk5x,
00598       UPPER   => UPPER_BOUND_A,
00599       LOWER   => LOWER_BOUND_A,
00600       VAL_IN  => oth_ewa2_bc ,
00601       VAL_OUT => open,
00602       IN_TIME => oth_hit_ewa2
00603       );
00604 
00605   oth_heinz_1 : timewindow
00606     port map
00607     (
00608       CLK     => clk5x,
00609       UPPER   => UPPER_BOUND_A,
00610       LOWER   => LOWER_BOUND_A,
00611       VAL_IN  => oth_heinz1_bc,
00612       VAL_OUT => open,
00613       IN_TIME => oth_hit_heinz1
00614       );
00615   oth_heinz_2 : timewindow
00616     port map
00617     (
00618       CLK     => clk5x,
00619       UPPER   => UPPER_BOUND_A,
00620       LOWER   => LOWER_BOUND_A,
00621       VAL_IN  => oth_heinz2_bc,
00622       VAL_OUT => open,
00623       IN_TIME => oth_hit_heinz2
00624       );
00625 
00626   oth_andrej_1 : timewindow
00627     port map
00628     (
00629       CLK     => clk5x,
00630       UPPER   => UPPER_BOUND_A,
00631       LOWER   => LOWER_BOUND_A,
00632       VAL_IN  => oth_andrej1_bc,
00633       VAL_OUT => open,
00634       IN_TIME => oth_hit_andrej1
00635       );
00636   oth_andrej_2 : timewindow
00637     port map
00638     (
00639       CLK     => clk5x,
00640       UPPER   => UPPER_BOUND_A,
00641       LOWER   => LOWER_BOUND_A,
00642       VAL_IN  => oth_andrej2_bc,
00643       VAL_OUT => open,
00644       IN_TIME => oth_hit_andrej2
00645       );
00646 
00647   oth_marko_1 : timewindow
00648     port map
00649     (
00650       CLK     => clk5x,
00651       UPPER   => UPPER_BOUND_C,
00652       LOWER   => LOWER_BOUND_C,
00653       VAL_IN  => oth_marko1_bc,
00654       VAL_OUT => open,
00655       IN_TIME => oth_hit_marko1
00656       );
00657   oth_marko_2 : timewindow
00658     port map
00659     (
00660       CLK     => clk5x,
00661       UPPER   => UPPER_BOUND_C,
00662       LOWER   => LOWER_BOUND_C,
00663       VAL_IN  => oth_marko2_bc,
00664       VAL_OUT => open,
00665       IN_TIME => oth_hit_marko2
00666       );
00667 
00668   oth_william_1 : timewindow
00669     port map
00670     (
00671       CLK     => clk5x,
00672       UPPER   => UPPER_BOUND_C,
00673       LOWER   => LOWER_BOUND_C,
00674       VAL_IN  => oth_william1_bc,
00675       VAL_OUT => open,
00676       IN_TIME => oth_hit_william1
00677       );
00678   oth_william_2 : timewindow
00679     port map
00680     (
00681       CLK     => clk5x,
00682       UPPER   => UPPER_BOUND_C,
00683       LOWER   => LOWER_BOUND_C,
00684       VAL_IN  => oth_william2_bc,
00685       VAL_OUT => open,
00686       IN_TIME => oth_hit_william2
00687       );
00688 
00689   oth_harris_1 : timewindow
00690     port map
00691     (
00692       CLK     => clk5x,
00693       UPPER   => UPPER_BOUND_C,
00694       LOWER   => LOWER_BOUND_C,
00695       VAL_IN  => oth_harris1_bc,
00696       VAL_OUT => open,
00697       IN_TIME => oth_hit_harris1
00698       );
00699   oth_harris_2 : timewindow
00700     port map
00701     (
00702       CLK     => clk5x,
00703       UPPER   => UPPER_BOUND_C,
00704       LOWER   => LOWER_BOUND_C,
00705       VAL_IN  => oth_harris2_bc,
00706       VAL_OUT => open,
00707       IN_TIME => oth_hit_harris2
00708       );
00709 
00710   oth_helmut_1 : timewindow
00711     port map
00712     (
00713       CLK     => clk5x,
00714       UPPER   => UPPER_BOUND_C,
00715       LOWER   => LOWER_BOUND_C,
00716       VAL_IN  => oth_helmut1_bc,
00717       VAL_OUT => open,
00718       IN_TIME => oth_hit_helmut1
00719       );
00720   oth_helmut_2 : timewindow
00721     port map
00722     (
00723       CLK     => clk5x,
00724       UPPER   => UPPER_BOUND_C,
00725       LOWER   => LOWER_BOUND_C,
00726       VAL_IN  => oth_helmut2_bc,
00727       VAL_OUT => open,
00728       IN_TIME => oth_hit_helmut2
00729       );
00730 
00731   -----------------------------------------------------------------------------
00732   -- C to A, local ROD
00733   -----------------------------------------------------------------------------
00734   Irena_11 : timewindow
00735     port map
00736     (
00737       CLK     => clk5x,
00738       UPPER   => UPPER_BOUND_A1,
00739       LOWER   => LOWER_BOUND_A1,
00740       VAL_IN  => irena1_bc,
00741       VAL_OUT => open,
00742       IN_TIME => hit_irena11 
00743       );
00744   Irena_21 : timewindow
00745     port map
00746     (
00747       CLK     => clk5x,
00748       UPPER   => UPPER_BOUND_A1,
00749       LOWER   => LOWER_BOUND_A1,
00750       VAL_IN  => irena2_bc,
00751       VAL_OUT => open,
00752       IN_TIME => hit_irena21 
00753       );
00754 
00755   ewa_11 : timewindow
00756     port map
00757     (
00758       CLK     => clk5x,
00759       UPPER   => UPPER_BOUND_A1,
00760       LOWER   => LOWER_BOUND_A1,
00761       VAL_IN  => ewa1_bc,
00762       VAL_OUT => open,
00763       IN_TIME => hit_ewa11
00764       );
00765   ewa_21 : timewindow
00766     port map
00767     (
00768       CLK     => clk5x,
00769       UPPER   => UPPER_BOUND_A1,
00770       LOWER   => LOWER_BOUND_A1,
00771       VAL_IN  => ewa2_bc,
00772       VAL_OUT => open,
00773       IN_TIME => hit_ewa21
00774       );
00775 
00776   heinz_11 : timewindow
00777     port map
00778     (
00779       CLK     => clk5x,
00780       UPPER   => UPPER_BOUND_A1,
00781       LOWER   => LOWER_BOUND_A1,
00782       VAL_IN  => heinz1_bc,
00783       VAL_OUT => open,
00784       IN_TIME => hit_heinz11 
00785       );
00786   heinz_21 : timewindow
00787     port map
00788     (
00789       CLK     => clk5x,
00790       UPPER   => UPPER_BOUND_A1,
00791       LOWER   => LOWER_BOUND_A1,
00792       VAL_IN  => heinz2_bc,
00793       VAL_OUT => open,
00794       IN_TIME => hit_heinz21 
00795       );
00796 
00797   andrej_11 : timewindow
00798     port map
00799     (
00800       CLK     => clk5x,
00801       UPPER   => UPPER_BOUND_A1,
00802       LOWER   => LOWER_BOUND_A1,
00803       VAL_IN  => andrej1_bc ,
00804       VAL_OUT => open,
00805       IN_TIME => hit_andrej11
00806       );
00807   andrej_21 : timewindow
00808     port map
00809     (
00810       CLK     => clk5x,
00811       UPPER   => UPPER_BOUND_A1,
00812       LOWER   => LOWER_BOUND_A1,
00813       VAL_IN  => andrej2_bc ,
00814       VAL_OUT => open,
00815       IN_TIME => hit_andrej21
00816       );
00817 
00818   marko_11 : timewindow
00819     port map
00820     (
00821       CLK     => clk5x,
00822       UPPER   => UPPER_BOUND_C1,
00823       LOWER   => LOWER_BOUND_C1,
00824       VAL_IN  => marko1_bc,
00825       VAL_OUT => open,
00826       IN_TIME => hit_marko11 
00827       );
00828   marko_21 : timewindow
00829     port map
00830     (
00831       CLK     => clk5x,
00832       UPPER   => UPPER_BOUND_C1,
00833       LOWER   => LOWER_BOUND_C1,
00834       VAL_IN  => marko2_bc,
00835       VAL_OUT => open,
00836       IN_TIME => hit_marko21 
00837       );
00838 
00839   william_11 : timewindow
00840     port map
00841     (
00842       CLK     => clk5x,
00843       UPPER   => UPPER_BOUND_C1,
00844       LOWER   => LOWER_BOUND_C1,
00845       VAL_IN  => william1_bc ,
00846       VAL_OUT => open,
00847       IN_TIME => hit_william11
00848       );
00849   william_21 : timewindow
00850     port map
00851     (
00852       CLK     => clk5x,
00853       UPPER   => UPPER_BOUND_C1,
00854       LOWER   => LOWER_BOUND_C1,
00855       VAL_IN  => william2_bc ,
00856       VAL_OUT => open,
00857       IN_TIME => hit_william21
00858       );
00859 
00860   harris_11 : timewindow
00861     port map
00862     (
00863       CLK     => clk5x,
00864       UPPER   => UPPER_BOUND_C1,
00865       LOWER   => LOWER_BOUND_C1,
00866       VAL_IN  => harris1_bc ,
00867       VAL_OUT => open,
00868       IN_TIME => hit_harris11
00869       );
00870   harris_21 : timewindow
00871     port map
00872     (
00873       CLK     => clk5x,
00874       UPPER   => UPPER_BOUND_C1,
00875       LOWER   => LOWER_BOUND_C1,
00876       VAL_IN  => harris2_bc ,
00877       VAL_OUT => open,
00878       IN_TIME => hit_harris21
00879       );
00880 
00881   helmut_11 : timewindow
00882     port map
00883     (
00884       CLK     => clk5x,
00885       UPPER   => UPPER_BOUND_C1,
00886       LOWER   => LOWER_BOUND_C1,
00887       VAL_IN  => helmut1_bc ,
00888       VAL_OUT => open,
00889       IN_TIME => hit_helmut11
00890       );
00891   helmut_21 : timewindow
00892     port map
00893     (
00894       CLK     => clk5x,
00895       UPPER   => UPPER_BOUND_C1,
00896       LOWER   => LOWER_BOUND_C1,
00897       VAL_IN  => helmut2_bc ,
00898       VAL_OUT => open,
00899       IN_TIME => hit_helmut21
00900       );
00901 
00902   -----------------------------------------------------------------------------
00903   -- C to A, remote ROD
00904   -----------------------------------------------------------------------------
00905   oth_Irena_11 : timewindow
00906     port map
00907     (
00908       CLK     => clk5x,
00909       UPPER   => UPPER_BOUND_A1,
00910       LOWER   => LOWER_BOUND_A1,
00911       VAL_IN  => oth_irena1_bc,
00912       VAL_OUT => open,
00913       IN_TIME => oth_hit_irena11
00914       );
00915   oth_Irena_21 : timewindow
00916     port map
00917     (
00918       CLK     => clk5x,
00919       UPPER   => UPPER_BOUND_A1,
00920       LOWER   => LOWER_BOUND_A1,
00921       VAL_IN  => oth_irena2_bc,
00922       VAL_OUT => open,
00923       IN_TIME => oth_hit_irena21
00924       );
00925 
00926   oth_ewa_11 : timewindow
00927     port map
00928     (
00929       CLK     => clk5x,
00930       UPPER   => UPPER_BOUND_A1,
00931       LOWER   => LOWER_BOUND_A1,
00932       VAL_IN  => oth_ewa1_bc ,
00933       VAL_OUT => open,
00934       IN_TIME => oth_hit_ewa11
00935       );
00936   oth_ewa_21 : timewindow
00937     port map
00938     (
00939       CLK     => clk5x,
00940       UPPER   => UPPER_BOUND_A1,
00941       LOWER   => LOWER_BOUND_A1,
00942       VAL_IN  => oth_ewa2_bc ,
00943       VAL_OUT => open,
00944       IN_TIME => oth_hit_ewa21
00945       );
00946 
00947   oth_heinz_11 : timewindow
00948     port map
00949     (
00950       CLK     => clk5x,
00951       UPPER   => UPPER_BOUND_A1,
00952       LOWER   => LOWER_BOUND_A1,
00953       VAL_IN  => oth_heinz1_bc,
00954       VAL_OUT => open,
00955       IN_TIME => oth_hit_heinz11
00956       );
00957   oth_heinz_21 : timewindow
00958     port map
00959     (
00960       CLK     => clk5x,
00961       UPPER   => UPPER_BOUND_A1,
00962       LOWER   => LOWER_BOUND_A1,
00963       VAL_IN  => oth_heinz2_bc,
00964       VAL_OUT => open,
00965       IN_TIME => oth_hit_heinz21
00966       );
00967 
00968   oth_andrej_11 : timewindow
00969     port map
00970     (
00971       CLK     => clk5x,
00972       UPPER   => UPPER_BOUND_A1,
00973       LOWER   => LOWER_BOUND_A1,
00974       VAL_IN  => oth_andrej1_bc,
00975       VAL_OUT => open,
00976       IN_TIME => oth_hit_andrej11
00977       );
00978   oth_andrej_21 : timewindow
00979     port map
00980     (
00981       CLK     => clk5x,
00982       UPPER   => UPPER_BOUND_A1,
00983       LOWER   => LOWER_BOUND_A1,
00984       VAL_IN  => oth_andrej2_bc,
00985       VAL_OUT => open,
00986       IN_TIME => oth_hit_andrej21
00987       );
00988 
00989   oth_marko_11 : timewindow
00990     port map
00991     (
00992       CLK     => clk5x,
00993       UPPER   => UPPER_BOUND_C1,
00994       LOWER   => LOWER_BOUND_C1,
00995       VAL_IN  => oth_marko1_bc,
00996       VAL_OUT => open,
00997       IN_TIME => oth_hit_marko11
00998       );
00999   oth_marko_21 : timewindow
01000     port map
01001     (
01002       CLK     => clk5x,
01003       UPPER   => UPPER_BOUND_C1,
01004       LOWER   => LOWER_BOUND_C1,
01005       VAL_IN  => oth_marko2_bc,
01006       VAL_OUT => open,
01007       IN_TIME => oth_hit_marko21
01008       );
01009 
01010   oth_william_11 : timewindow
01011     port map
01012     (
01013       CLK     => clk5x,
01014       UPPER   => UPPER_BOUND_C1,
01015       LOWER   => LOWER_BOUND_C1,
01016       VAL_IN  => oth_william1_bc,
01017       VAL_OUT => open,
01018       IN_TIME => oth_hit_william11
01019       );
01020   oth_william_21 : timewindow
01021     port map
01022     (
01023       CLK     => clk5x,
01024       UPPER   => UPPER_BOUND_C1,
01025       LOWER   => LOWER_BOUND_C1,
01026       VAL_IN  => oth_william2_bc,
01027       VAL_OUT => open,
01028       IN_TIME => oth_hit_william21
01029       );
01030 
01031   oth_harris_11 : timewindow
01032     port map
01033     (
01034       CLK     => clk5x,
01035       UPPER   => UPPER_BOUND_C1,
01036       LOWER   => LOWER_BOUND_C1,
01037       VAL_IN  => oth_harris1_bc,
01038       VAL_OUT => open,
01039       IN_TIME => oth_hit_harris11
01040       );
01041   oth_harris_21 : timewindow
01042     port map
01043     (
01044       CLK     => clk5x,
01045       UPPER   => UPPER_BOUND_C1,
01046       LOWER   => LOWER_BOUND_C1,
01047       VAL_IN  => oth_harris2_bc,
01048       VAL_OUT => open,
01049       IN_TIME => oth_hit_harris21
01050       );
01051 
01052   oth_helmut_11 : timewindow
01053     port map
01054     (
01055       CLK     => clk5x,
01056       UPPER   => UPPER_BOUND_C1,
01057       LOWER   => LOWER_BOUND_C1,
01058       VAL_IN  => oth_helmut1_bc,
01059       VAL_OUT => open,
01060       IN_TIME => oth_hit_helmut11
01061       );
01062   oth_helmut_21 : timewindow
01063     port map
01064     (
01065       CLK     => clk5x,
01066       UPPER   => UPPER_BOUND_C1,
01067       LOWER   => LOWER_BOUND_C1,
01068       VAL_IN  => oth_helmut2_bc,
01069       VAL_OUT => open,
01070       IN_TIME => oth_hit_helmut21
01071       );
01072 
01073   -----------------------------------------------------------------------------
01074   -- wide cut, local ROD
01075   -----------------------------------------------------------------------------
01076   Irena_1w : timewindow
01077     port map
01078     (
01079       CLK     => clk5x,
01080       UPPER   => UPPER_BOUND_Aw,
01081       LOWER   => LOWER_BOUND_Aw,
01082       VAL_IN  => irena1_bc,
01083       VAL_OUT => open,
01084       IN_TIME => hit_irena1w 
01085       );
01086   Irena_2w : timewindow
01087     port map
01088     (
01089       CLK     => clk5x,
01090       UPPER   => UPPER_BOUND_Aw,
01091       LOWER   => LOWER_BOUND_Aw,
01092       VAL_IN  => irena2_bc,
01093       VAL_OUT => open,
01094       IN_TIME => hit_irena2w 
01095       );
01096 
01097   ewa_1w : timewindow
01098     port map
01099     (
01100       CLK     => clk5x,
01101       UPPER   => UPPER_BOUND_Aw,
01102       LOWER   => LOWER_BOUND_Aw,
01103       VAL_IN  => ewa1_bc,
01104       VAL_OUT => open,
01105       IN_TIME => hit_ewa1w
01106       );
01107   ewa_2w : timewindow
01108     port map
01109     (
01110       CLK     => clk5x,
01111       UPPER   => UPPER_BOUND_Aw,
01112       LOWER   => LOWER_BOUND_Aw,
01113       VAL_IN  => ewa2_bc,
01114       VAL_OUT => open,
01115       IN_TIME => hit_ewa2w
01116       );
01117 
01118   heinz_1w : timewindow
01119     port map
01120     (
01121       CLK     => clk5x,
01122       UPPER   => UPPER_BOUND_Aw,
01123       LOWER   => LOWER_BOUND_Aw,
01124       VAL_IN  => heinz1_bc,
01125       VAL_OUT => open,
01126       IN_TIME => hit_heinz1w 
01127       );
01128   heinz_2w : timewindow
01129     port map
01130     (
01131       CLK     => clk5x,
01132       UPPER   => UPPER_BOUND_Aw,
01133       LOWER   => LOWER_BOUND_Aw,
01134       VAL_IN  => heinz2_bc,
01135       VAL_OUT => open,
01136       IN_TIME => hit_heinz2w 
01137       );
01138 
01139   andrej_1w : timewindow
01140     port map
01141     (
01142       CLK     => clk5x,
01143       UPPER   => UPPER_BOUND_Aw,
01144       LOWER   => LOWER_BOUND_Aw,
01145       VAL_IN  => andrej1_bc ,
01146       VAL_OUT => open,
01147       IN_TIME => hit_andrej1w
01148       );
01149   andrej_2w : timewindow
01150     port map
01151     (
01152       CLK     => clk5x,
01153       UPPER   => UPPER_BOUND_Aw,
01154       LOWER   => LOWER_BOUND_Aw,
01155       VAL_IN  => andrej2_bc ,
01156       VAL_OUT => open,
01157       IN_TIME => hit_andrej2w
01158       );
01159 
01160   marko_1w : timewindow
01161     port map
01162     (
01163       CLK     => clk5x,
01164       UPPER   => UPPER_BOUND_Cw,
01165       LOWER   => LOWER_BOUND_Cw,
01166       VAL_IN  => marko1_bc,
01167       VAL_OUT => open,
01168       IN_TIME => hit_marko1w 
01169       );
01170   marko_2w : timewindow
01171     port map
01172     (
01173       CLK     => clk5x,
01174       UPPER   => UPPER_BOUND_Cw,
01175       LOWER   => LOWER_BOUND_Cw,
01176       VAL_IN  => marko2_bc,
01177       VAL_OUT => open,
01178       IN_TIME => hit_marko2w 
01179       );
01180 
01181   william_1w : timewindow
01182     port map
01183     (
01184       CLK     => clk5x,
01185       UPPER   => UPPER_BOUND_Cw,
01186       LOWER   => LOWER_BOUND_Cw,
01187       VAL_IN  => william1_bc ,
01188       VAL_OUT => open,
01189       IN_TIME => hit_william1w
01190       );
01191   william_2w : timewindow
01192     port map
01193     (
01194       CLK     => clk5x,
01195       UPPER   => UPPER_BOUND_Cw,
01196       LOWER   => LOWER_BOUND_Cw,
01197       VAL_IN  => william2_bc ,
01198       VAL_OUT => open,
01199       IN_TIME => hit_william2w
01200       );
01201 
01202   harris_1w : timewindow
01203     port map
01204     (
01205       CLK     => clk5x,
01206       UPPER   => UPPER_BOUND_Cw,
01207       LOWER   => LOWER_BOUND_Cw,
01208       VAL_IN  => harris1_bc ,
01209       VAL_OUT => open,
01210       IN_TIME => hit_harris1w
01211       );
01212   harris_2w : timewindow
01213     port map
01214     (
01215       CLK     => clk5x,
01216       UPPER   => UPPER_BOUND_Cw,
01217       LOWER   => LOWER_BOUND_Cw,
01218       VAL_IN  => harris2_bc ,
01219       VAL_OUT => open,
01220       IN_TIME => hit_harris2w
01221       );
01222 
01223   helmut_1w : timewindow
01224     port map
01225     (
01226       CLK     => clk5x,
01227       UPPER   => UPPER_BOUND_Cw,
01228       LOWER   => LOWER_BOUND_Cw,
01229       VAL_IN  => helmut1_bc ,
01230       VAL_OUT => open,
01231       IN_TIME => hit_helmut1w
01232       );
01233   helmut_2w : timewindow
01234     port map
01235     (
01236       CLK     => clk5x,
01237       UPPER   => UPPER_BOUND_Cw,
01238       LOWER   => LOWER_BOUND_Cw,
01239       VAL_IN  => helmut2_bc ,
01240       VAL_OUT => open,
01241       IN_TIME => hit_helmut2w
01242       );
01243 
01244   -----------------------------------------------------------------------------
01245   -- wide cut, remote ROD
01246   -----------------------------------------------------------------------------
01247   oth_Irena_1w : timewindow
01248     port map
01249     (
01250       CLK     => clk5x,
01251       UPPER   => UPPER_BOUND_Aw,
01252       LOWER   => LOWER_BOUND_Aw,
01253       VAL_IN  => oth_irena1_bc,
01254       VAL_OUT => open,
01255       IN_TIME => oth_hit_irena1w
01256       );
01257   oth_Irena_2w : timewindow
01258     port map
01259     (
01260       CLK     => clk5x,
01261       UPPER   => UPPER_BOUND_Aw,
01262       LOWER   => LOWER_BOUND_Aw,
01263       VAL_IN  => oth_irena2_bc,
01264       VAL_OUT => open,
01265       IN_TIME => oth_hit_irena2w
01266       );
01267 
01268   oth_ewa_1w : timewindow
01269     port map
01270     (
01271       CLK     => clk5x,
01272       UPPER   => UPPER_BOUND_Aw,
01273       LOWER   => LOWER_BOUND_Aw,
01274       VAL_IN  => oth_ewa1_bc ,
01275       VAL_OUT => open,
01276       IN_TIME => oth_hit_ewa1w
01277       );
01278   oth_ewa_2w : timewindow
01279     port map
01280     (
01281       CLK     => clk5x,
01282       UPPER   => UPPER_BOUND_Aw,
01283       LOWER   => LOWER_BOUND_Aw,
01284       VAL_IN  => oth_ewa2_bc ,
01285       VAL_OUT => open,
01286       IN_TIME => oth_hit_ewa2w
01287       );
01288 
01289   oth_heinz_1w : timewindow
01290     port map
01291     (
01292       CLK     => clk5x,
01293       UPPER   => UPPER_BOUND_Aw,
01294       LOWER   => LOWER_BOUND_Aw,
01295       VAL_IN  => oth_heinz1_bc,
01296       VAL_OUT => open,
01297       IN_TIME => oth_hit_heinz1w
01298       );
01299   oth_heinz_2w : timewindow
01300     port map
01301     (
01302       CLK     => clk5x,
01303       UPPER   => UPPER_BOUND_Aw,
01304       LOWER   => LOWER_BOUND_Aw,
01305       VAL_IN  => oth_heinz2_bc,
01306       VAL_OUT => open,
01307       IN_TIME => oth_hit_heinz2w
01308       );
01309 
01310   oth_andrej_1w : timewindow
01311     port map
01312     (
01313       CLK     => clk5x,
01314       UPPER   => UPPER_BOUND_Aw,
01315       LOWER   => LOWER_BOUND_Aw,
01316       VAL_IN  => oth_andrej1_bc,
01317       VAL_OUT => open,
01318       IN_TIME => oth_hit_andrej1w
01319       );
01320   oth_andrej_2w : timewindow
01321     port map
01322     (
01323       CLK     => clk5x,
01324       UPPER   => UPPER_BOUND_Aw,
01325       LOWER   => LOWER_BOUND_Aw,
01326       VAL_IN  => oth_andrej2_bc,
01327       VAL_OUT => open,
01328       IN_TIME => oth_hit_andrej2w
01329       );
01330 
01331   oth_marko_1w : timewindow
01332     port map
01333     (
01334       CLK     => clk5x,
01335       UPPER   => UPPER_BOUND_Cw,
01336       LOWER   => LOWER_BOUND_Cw,
01337       VAL_IN  => oth_marko1_bc,
01338       VAL_OUT => open,
01339       IN_TIME => oth_hit_marko1w
01340       );
01341   oth_marko_2w : timewindow
01342     port map
01343     (
01344       CLK     => clk5x,
01345       UPPER   => UPPER_BOUND_Cw,
01346       LOWER   => LOWER_BOUND_Cw,
01347       VAL_IN  => oth_marko2_bc,
01348       VAL_OUT => open,
01349       IN_TIME => oth_hit_marko2w
01350       );
01351 
01352   oth_william_1w : timewindow
01353     port map
01354     (
01355       CLK     => clk5x,
01356       UPPER   => UPPER_BOUND_Cw,
01357       LOWER   => LOWER_BOUND_Cw,
01358       VAL_IN  => oth_william1_bc,
01359       VAL_OUT => open,
01360       IN_TIME => oth_hit_william1w
01361       );
01362   oth_william_2w : timewindow
01363     port map
01364     (
01365       CLK     => clk5x,
01366       UPPER   => UPPER_BOUND_Cw,
01367       LOWER   => LOWER_BOUND_Cw,
01368       VAL_IN  => oth_william2_bc,
01369       VAL_OUT => open,
01370       IN_TIME => oth_hit_william2w
01371       );
01372 
01373   oth_harris_1w : timewindow
01374     port map
01375     (
01376       CLK     => clk5x,
01377       UPPER   => UPPER_BOUND_Cw,
01378       LOWER   => LOWER_BOUND_Cw,
01379       VAL_IN  => oth_harris1_bc,
01380       VAL_OUT => open,
01381       IN_TIME => oth_hit_harris1w
01382       );
01383   oth_harris_2w : timewindow
01384     port map
01385     (
01386       CLK     => clk5x,
01387       UPPER   => UPPER_BOUND_Cw,
01388       LOWER   => LOWER_BOUND_Cw,
01389       VAL_IN  => oth_harris2_bc,
01390       VAL_OUT => open,
01391       IN_TIME => oth_hit_harris2w
01392       );
01393 
01394   oth_helmut_1w : timewindow
01395     port map
01396     (
01397       CLK     => clk5x,
01398       UPPER   => UPPER_BOUND_Cw,
01399       LOWER   => LOWER_BOUND_Cw,
01400       VAL_IN  => oth_helmut1_bc,
01401       VAL_OUT => open,
01402       IN_TIME => oth_hit_helmut1w
01403       );
01404   oth_helmut_2w : timewindow
01405     port map
01406     (
01407       CLK     => clk5x,
01408       UPPER   => UPPER_BOUND_Cw,
01409       LOWER   => LOWER_BOUND_Cw,
01410       VAL_IN  => oth_helmut2_bc,
01411       VAL_OUT => open,
01412       IN_TIME => oth_hit_helmut2w
01413       );
01414 
01415   -----------------------------------------------------------------------------
01416   -- Multiplicity counting
01417   -----------------------------------------------------------------------------
01418   mult1 : if kRODconf = "0" generate
01419     mult_c1 <= hit_marko + hit_william;
01420     mult_c2 <= oth_hit_harris + oth_hit_helmut;
01421     mult_a1 <= hit_irena + hit_ewa;
01422     mult_a2 <= oth_hit_andrej + oth_hit_heinz;
01423   end generate mult1;
01424   mult2 : if kRODconf = "1" generate
01425     mult_c1 <= oth_hit_marko + oth_hit_william;
01426     mult_c2 <= hit_harris + hit_helmut;
01427     mult_a1 <= oth_hit_irena + oth_hit_ewa;
01428     mult_a2 <= hit_andrej + hit_heinz;
01429   end generate mult2;
01430 
01431   mult_c <= "11" when (mult_c1(0) and mult_c1(1) and mult_c2(0) and mult_c2(1)) = '1' else
01432             mult_c1 + mult_c2;
01433   mult_a <= "11" when (mult_a1(0) and mult_a1(1) and mult_a2(0) and mult_a2(1)) = '1' else
01434             mult_a1 + mult_a2;
01435   
01436   BCM_C <= mult_c when rising_edge(clk5x);
01437   BCM_A <= mult_a when rising_edge(clk5x);
01438 
01439   -----------------------------------------------------------------------------
01440   -- Attenuated Channels
01441   -----------------------------------------------------------------------------
01442   att1 : if kRODconf = "0" generate
01443     hit_atta <= hit_irena(0) or hit_andrej(0) or
01444                 oth_hit_ewa(0) or oth_hit_heinz(0);
01445     hit_attc <= hit_william(0) or hit_harris(0) or
01446                 oth_hit_marko(0) or oth_hit_helmut(0);
01447   end generate att1;
01448   att2 : if kRODconf = "1" generate
01449     hit_atta <= oth_hit_irena(0) or oth_hit_andrej(0) or
01450                 hit_ewa(0) or hit_heinz(0);
01451     hit_attc <= oth_hit_william(0) or oth_hit_harris(0) or
01452                 hit_marko(0) or hit_helmut(0);
01453   end generate att2;
01454   BCM_AttHitA <= hit_atta when rising_edge(clk5x);
01455   BCM_AttHitC <= hit_attc when rising_edge(clk5x);
01456 
01457   -----------------------------------------------------------------------------
01458   -- In-Time & Out-of-Time coincidences
01459   -----------------------------------------------------------------------------
01460   wide_c <= hit_marko1w or hit_marko2w or hit_helmut1w or hit_helmut2w or
01461             hit_harris1w or hit_harris2w or hit_william1w or hit_william2w or
01462             oth_hit_marko1w or oth_hit_marko2w or oth_hit_helmut1w or oth_hit_helmut2w or
01463             oth_hit_harris1w or oth_hit_harris2w or oth_hit_william1w or oth_hit_william2w;
01464   wide_a <= hit_irena1w or hit_irena2w or hit_ewa1w or hit_ewa2w or
01465             hit_andrej1w or hit_andrej2w or hit_heinz1w or hit_heinz2w or
01466             oth_hit_irena1w or oth_hit_irena2w or oth_hit_ewa1w or oth_hit_ewa2w or
01467             oth_hit_andrej1w or oth_hit_andrej2w or oth_hit_heinz1w or oth_hit_heinz2w;
01468   BCM_wide <= wide_a and wide_c when rising_edge(clk5x);
01469 
01470   ctoa_c <= hit_marko11 or hit_marko21 or hit_helmut11 or hit_helmut21 or
01471             hit_harris11 or hit_harris21 or hit_william11 or hit_william21 or
01472             oth_hit_marko11 or oth_hit_marko21 or oth_hit_helmut11 or oth_hit_helmut21 or
01473             oth_hit_harris11 or oth_hit_harris21 or oth_hit_william11 or oth_hit_william21;
01474   ctoa_a <= hit_irena11 or hit_irena21 or hit_ewa11 or hit_ewa21 or
01475             hit_andrej11 or hit_andrej21 or hit_heinz11 or hit_heinz21 or
01476             oth_hit_irena11 or oth_hit_irena21 or oth_hit_ewa11 or oth_hit_ewa21 or
01477             oth_hit_andrej11 or oth_hit_andrej21 or oth_hit_heinz11 or oth_hit_heinz21;
01478   BCM_CtoA <= ctoa_a and ctoa_c when rising_edge(clk5x);
01479 
01480   atoc_c <= hit_marko1 or hit_marko2 or hit_helmut1 or hit_helmut2 or
01481             hit_harris1 or hit_harris2 or hit_william1 or hit_william2 or
01482             oth_hit_marko1 or oth_hit_marko2 or oth_hit_helmut1 or oth_hit_helmut2 or
01483             oth_hit_harris1 or oth_hit_harris2 or oth_hit_william1 or oth_hit_william2;
01484   atoc_a <= hit_irena1 or hit_irena2 or hit_ewa1 or hit_ewa2 or
01485             hit_andrej1 or hit_andrej2 or hit_heinz1 or hit_heinz2 or
01486             oth_hit_irena1 or oth_hit_irena2 or oth_hit_ewa1 or oth_hit_ewa2 or
01487             oth_hit_andrej1 or oth_hit_andrej2 or oth_hit_heinz1 or oth_hit_heinz2;
01488   BCM_AtoC <= atoc_a and atoc_c when rising_edge(clk5x);
01489 
01490   -----------------------------------------------------------------------------
01491   -- Output assignments
01492   -----------------------------------------------------------------------------
01493   CTP_OUT(1) <= BCM_AtoC;
01494   CTP_OUT(2) <= BCM_CtoA;
01495   CTP_OUT(3) <= BCM_wide;
01496   CTP_OUT(4) <= BCM_A(0);
01497   CTP_OUT(5) <= BCM_A(1);
01498   CTP_OUT(6) <= BCM_C(0);
01499   CTP_OUT(7) <= BCM_C(1);
01500   CTP_OUT(8) <= BCM_AttHitA;
01501   CTP_OUT(9) <= BCM_AttHitC;
01502   
01503 end ctp_logic_arc;