bcm_rod_treadmil.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/rod/bcm_rod_treadmil.vhd,v $                                                  *
--*  $Revision: 1.11.2.4 $                                         *
--*  $Name: dev $                                              *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:48 $                              *


--*                                                            *
--**************************************************************
----------------------------------------------------------------------------------
-- Company:         CERN
-- Engineer:       Daniel Dobos
-- 
-- Create Date:    18:24:50 11/20/2007 
-- Design Name: 
-- Module Name:    bcm_rod_treadmil - bcm_rod_treadmil_arc 
-- Project Name:   bcm_rod
-- Target Devices: 
-- Tool versions: 
-- Description: 
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;









entity bcm_rod_treadmil is
  port (
    CLK_2X                : in  std_logic;
    SCLR                  : in  std_logic;
    data_input            : in  std_logic_vector(223 downto 0);
    data_input_valid      : in  std_logic;
    data_input_endoffrag  : in  std_logic;
    stop                  : in  std_logic;
    data_output           : out std_logic_vector(31 downto 0);
    data_output_valid     : out std_logic;
    data_output_endoffrag : out std_logic;
    busy                  : out std_logic;
    error                 : out std_logic
    );
end bcm_rod_treadmil;









architecture bcm_rod_treadmil_arc of bcm_rod_treadmil is

  signal shift_register     : std_logic_vector(223 downto 0) := (others => '0');
  signal eof_shift_register : std_logic_vector(6 downto 0)   := (others => '0');
  signal fill_counter       : std_logic_vector(2 downto 0)   := (others => '0');
  signal intern_input_valid : std_logic                      := '0';
  signal last_input_valid   : std_logic                      := '0';
  signal last_error         : std_logic                      := '0';
  signal error_block        : std_logic                      := '0';
  signal last_eof           : std_logic                      := '1';

begin


  shift : process (CLK_2X)
  begin
    if (CLK_2X'event and CLK_2X = '1') then
      if (SCLR = '1') then              -- synchronous clear (reset)
        data_output           <= (others => '0');
        data_output_valid     <= '0';
        data_output_endoffrag <= '0';
        busy                  <= '1';
        error                 <= '0';
        shift_register        <= (others => '0');
        eof_shift_register    <= (others => '0');
        fill_counter          <= (others => '0');
        intern_input_valid    <= '0';
        last_input_valid      <= '0';
        last_error            <= '0';
        error_block           <= '0';
        last_eof              <= '1';
      else
        intern_input_valid <= data_input_valid;
        last_input_valid   <= intern_input_valid;
        if (data_input_valid = '1' and last_input_valid = '0' and fill_counter = "000") then  -- shift register empty and data to fill available
          if (stop = '0') then  -- output not stopped - can put first word directly to output and store rest in shift register
            data_output_valid     <= '1';
            data_output_endoffrag <= '0';
            if (last_eof = '1') then
              data_output        <= data_input(31 downto 0);
              shift_register     <= X"00000000" & data_input(223 downto 32);
              eof_shift_register <= "0" & data_input_endoffrag & "00000";
              fill_counter       <= "110";
            else                        -- skip LVL1ID
              data_output        <= data_input(63 downto 32);
              shift_register     <= X"00000000_00000000" & data_input(223 downto 64);
              eof_shift_register <= "00" & data_input_endoffrag & "0000";
              fill_counter       <= "101";
            end if;
          else  -- output stopped - store entire input in shift register
            data_output           <= (others => '0');
            data_output_valid     <= '0';
            data_output_endoffrag <= '0';
            if (last_eof = '1') then
              shift_register     <= data_input(223 downto 0);
              eof_shift_register <= data_input_endoffrag & "000000";
              fill_counter       <= "111";
            else                        -- skip LVL1ID
              shift_register     <= X"00000000" & data_input(223 downto 32);
              eof_shift_register <= "0" & data_input_endoffrag & "00000";
              fill_counter       <= "110";
            end if;
          end if;
          last_eof    <= data_input_endoffrag;
          busy        <= '1';
          error       <= '0';  -- data could be stored in shift register
          last_error  <= '0';           -- new data block, clear error latch
          error_block <= '1';  -- to avoid error in 2nd data_input_valid pulse clock cycle
        elsif (not (fill_counter = "000")) then  -- shift register not empty
          if (stop = '0') then          -- output not stopped - shift out data
            data_output           <= shift_register(31 downto 0);
            data_output_valid     <= '1';
            data_output_endoffrag <= eof_shift_register(0);
            shift_register        <= X"00000000" & shift_register(223 downto 32);
            eof_shift_register    <= "0" & eof_shift_register(6 downto 1);
            fill_counter          <= fill_counter - "1"; 
          else  -- output stopped - do not shift out data
            data_output           <= (others => '0');
            data_output_valid     <= '0';
            data_output_endoffrag <= '0';
            shift_register        <= shift_register;
            eof_shift_register    <= eof_shift_register;
            fill_counter          <= fill_counter;
          end if;
          busy <= '1';
          if (data_input_valid = '1' and error_block = '0') then  -- data to fill available but shift register not empty and not 2nd data_input_valid pulse clock cycle
            error      <= '1';  -- data could not be stored in shift register
            last_error <= '1';          -- set error latch
          else                          -- keep error state if error latched 
            error      <= last_error;
            last_error <= last_error;
          end if;
          error_block <= '0';
        else    -- shift register empty and no data to fill available
          data_output           <= (others => '0');
          data_output_valid     <= '0';
          data_output_endoffrag <= '0';
          busy                  <= '0';
          error                 <= '0';
          shift_register        <= (others => '0');
          fill_counter          <= (others => '0');
          last_error            <= '0';
          error_block           <= '0';
        end if;
      end if;
    end if;
  end process shift;

end bcm_rod_treadmil_arc;

---

Author: M.Niegl

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