BCM-AAA: mem_interface_top_ddr_controller

00001 --**************************************************************
00002 --*                                                            *
00003 --*     The source code for the ATLAS BCM "AAA" FPGA is made   *
00004 --*     available via the GNU General Public License (GPL)     *
00005 --*     unless otherwise stated below.                         *
00006 --*                                                            *
00007 --*     In case of problems/questions/bug reports etc. please  *
00008 --*     contact michael.niegl@cern.ch                          *
00009 --*                                                            *
00010 --**************************************************************
00011 
00012 --**************************************************************
00013 --*                                                            *
00014 --*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr/mem_interface_top_ddr_controller_0.vhd,v $                                                  *
00015 --*  $Revision: 1.3.2.3 $                                                *
00016 --*  $Name: dev $                                                    *
00017 --*  $Author: mniegl $                                                  *
00018 --*  $Date: 2008/11/03 17:57:43 $                                                    *
00019 --*                                                            *
00020 --**************************************************************
00021 -------------------------------------------------------------------------------
00022 -- Copyright (c) 2005 Xilinx, Inc.
00023 -- This design is confidential and proprietary of Xilinx, All Rights Reserved.
00024 -------------------------------------------------------------------------------
00025 --   ____  ____
00026 --  /   /\/   /
00027 -- /___/  \  / Vendor: Xilinx
00028 -- \   \   \/ Version: 1.6
00029 --  \   \ Application : MIG
00030 --  /   / Filename: mem_interface_top_ddr_controller_0.vhd
00031 -- /___/   /\ Date Last Modified:  Wed Jun 1 2005
00032 -- \   \  /  \Date Created: Mon May 2 2005
00033 --  \___\/\___\
00034 -- Device: Virtex-4
00035 -- Design Name: DDR1_SDRAM
00036 -- Description: This is the main control logic of the memory interface. All commands
00037 --              are issued from here acoording to the burst, CAS Latency and the
00038 --              user commands.
00039 -------------------------------------------------------------------------------
00040 
00041 
00042 library ieee;
00043 
00044 use ieee.std_logic_1164.all;
00045 
00046 use ieee.std_logic_unsigned.all;
00047 
00048 library unisim;
00049 
00050 use unisim.vcomponents.all;
00051 use work.mem_interface_top_parameters_0.all;
00052 
00053 entity mem_interface_top_ddr_controller_0 is
00054         port( 
00055                 clk_0                   : in std_logic; 
00056                 refresh_clk             : in std_logic; 
00057                 rst                     : in std_logic; 
00058                 -- FIFO  signals
00059                 af_addr                 : in std_logic_vector(35 downto 0);
00060                 af_empty                : in std_logic; 
00061                 --  signals for the Dummy Reads
00062                 comp_done               : in std_logic;
00063                 phy_Dly_Slct_Done       : in std_logic; 
00064                 ctrl_Dummyread_Start    : out std_logic;
00065                 -- FIFO read enable signals
00066                 ctrl_af_RdEn            : out std_logic;
00067                 ctrl_Wdf_RdEn           : out std_logic;
00068                 -- Rst and Enable signals for DQS logic
00069                 ctrl_Dqs_Rst            : out std_logic;
00070                 ctrl_Dqs_En             : out std_logic;
00071                 -- Read and Write Enable signals to the phy interface
00072                 ctrl_WrEn               : out std_logic;
00073                 ctrl_RdEn               : out std_logic;
00074                 --    
00075                 ctrl_ddr_address        : out std_logic_vector((row_address - 1) downto 0);
00076                 ctrl_ddr_ba             : out std_logic_vector((bank_address - 1) downto 0);
00077                 ctrl_ddr_ras_L          : out std_logic;
00078                 ctrl_ddr_cas_L          : out std_logic;
00079                 ctrl_ddr_we_L           : out std_logic;
00080                 ctrl_ddr_cs_L           : out std_logic;
00081                 ctrl_ddr_cke            : out std_logic;
00082                 dummy_write_pattern     : out std_logic;
00083                 burst_length            : out std_logic_vector(2 downto 0)
00084             );
00085 end mem_interface_top_ddr_controller_0;
00086 
00087 architecture arch of mem_interface_top_ddr_controller_0 is
00088 
00089 signal init_count               : std_logic_vector(3 downto 0);       
00090 signal init_count_cp            : std_logic_vector(3 downto 0);    
00091 signal init_memory              : std_logic;      
00092 signal count_200_cycle          : std_logic_vector(7 downto 0);  
00093 signal ref_flag                 : std_logic;        
00094 signal ref_flag_266             : std_logic;     
00095 signal ref_flag_266_r           : std_logic;   
00096 signal auto_ref                 : std_logic;         
00097 signal next_state               : std_logic_vector(4 downto 0);       
00098 signal state                    : std_logic_vector(4 downto 0);            
00099 signal state_r2                 : std_logic_vector(4 downto 0);         
00100 signal state_r3                 : std_logic_vector(4 downto 0);
00101 signal row_addr_r               : std_logic_vector((row_address - 1) downto 0);                        
00102 signal ddr_address_init_r       : std_logic_vector((row_address - 1) downto 0);  
00103 signal ddr_address_r1           : std_logic_vector((row_address - 1) downto 0);                    
00104 signal ddr_ba_r1                : std_logic_vector((bank_address - 1) downto 0);                         
00105 signal mrd_count                : std_logic;                  
00106 signal rp_count                 : std_logic_vector(2 downto 0);                   
00107 signal rfc_count                : std_logic_vector(5 downto 0);                  
00108 signal rcd_count                : std_logic_vector(2 downto 0);                  
00109 signal ras_count                : std_logic_vector(3 downto 0);                  
00110 signal wr_to_rd_count           : std_logic_vector(3 downto 0);             
00111 signal rd_to_wr_count           : std_logic_vector(3 downto 0);             
00112 signal rtp_count                : std_logic_vector(3 downto 0);                  
00113 signal wtp_count                : std_logic_vector(3 downto 0);                  
00114 signal refi_count               : std_logic_vector((max_ref_width - 1) downto 0);                 
00115 signal cas_count                : std_logic_vector(2 downto 0);                  
00116 signal cas_check_count          : std_logic_vector(3 downto 0);            
00117 signal wrburst_cnt              : std_logic_vector(2 downto 0);                
00118 signal read_burst_cnt           : std_logic_vector(2 downto 0);             
00119 signal ctrl_WrEn_cnt            : std_logic_vector(2 downto 0);              
00120 signal rdburst_cnt              : std_logic_vector(2 downto 0);                
00121 signal af_addr_r                : std_logic_vector(35 downto 0);                  
00122 signal af_addr_r1               : std_logic_vector(35 downto 0);                 
00123 signal wdf_rden_r               : std_logic;                 
00124 signal wdf_rden_r2              : std_logic;                
00125 signal wdf_rden_r3              : std_logic;                
00126 signal wdf_rden_r4              : std_logic;                
00127 signal af_rden                  : std_logic;                   
00128 signal ddr_ras_r2               : std_logic;                 
00129 signal ddr_cas_r2               : std_logic;                 
00130 signal ddr_we_r2                : std_logic;                  
00131 signal ddr_ras_r                : std_logic;                  
00132 signal ddr_cas_r                : std_logic;                  
00133 signal ddr_we_r                 : std_logic;                   
00134 signal ddr_ras_r3               : std_logic;                 
00135 signal ddr_cas_r3               : std_logic;                 
00136 signal ddr_we_r3                : std_logic;                  
00137 signal idle_cnt                 : std_logic_vector(3 downto 0);                   
00138 signal ctrl_Dummyread_Start_r1  : std_logic;   
00139 signal ctrl_Dummyread_Start_r2  : std_logic;   
00140 signal ctrl_Dummyread_Start_r3  : std_logic;   
00141 signal ctrl_Dummyread_Start_r4  : std_logic;   
00142 signal conflict_resolved_r      : std_logic;       
00143 signal ddr_cke_r                : std_logic;  
00144 signal chip_cnt                 : std_logic_vector(1 downto 0);  
00145 signal dummy_read_en            : std_logic;        
00146 signal ctrl_init_done           : std_logic;       
00147 signal count_200cycle_done_r    : std_logic;  
00148 signal init_done                : std_logic;         
00149 signal burst_cnt                : std_logic_vector(3 downto 0); 
00150 signal burst_cnt_by2            : std_logic_vector(2 downto 0);
00151 signal conflict_detect          : std_logic;  
00152 signal conflict_detect_r        : std_logic;
00153 signal load_mode_reg            : std_logic_vector((row_address - 1) downto 0);
00154 signal ext_mode_reg             : std_logic_vector((row_address - 1) downto 0); 
00155 signal CAS_LATENCY_VALUE        : std_logic_vector(3 downto 0);   
00156 signal BURST_LENGTH_VALUE       : std_logic_vector(2 downto 0);
00157 signal REGISTERED_VALUE         : std_logic;    
00158 signal ECC_VALUE                : std_logic;           
00159 signal WR                       : std_logic;  
00160 signal RD                       : std_logic;  
00161 signal LMR                      : std_logic;
00162 signal PRE                      : std_logic; 
00163 signal REF                      : std_logic; 
00164 signal ACT                      : std_logic; 
00165 signal WR_r                     : std_logic;                 
00166 signal RD_r                     : std_logic;                 
00167 signal LMR_r                    : std_logic;               
00168 signal PRE_r                    : std_logic;                
00169 signal REF_r                    : std_logic;                
00170 signal ACT_r                    : std_logic;                
00171 signal af_empty_r               : std_logic;           
00172 signal LMR_PRE_REF_ACT_cmd_r    : std_logic;
00173 signal command_address          : std_logic_vector(2 downto 0);      
00174 signal zeroes                   : std_logic_vector((row_address - col_ap_width) downto 0);               
00175 signal cke_200us_cnt            : std_logic_vector(4 downto 0);  
00176 signal done_200us               : std_logic;  
00177 signal write_state              : std_logic;         
00178 signal read_state               : std_logic;          
00179 signal read_write_state         : std_logic;    
00180 signal burst_write_state        : std_logic;   
00181 signal first_write_state        : std_logic;   
00182 signal burst_read_state         : std_logic;    
00183 signal first_read_state         : std_logic;    
00184 signal burst_read_state_r2      : std_logic; 
00185 signal burst_read_state_r3      : std_logic; 
00186 signal first_read_state_r2      : std_logic; 
00187 signal read_write_state_r2      : std_logic; 
00188 signal read_write_state_r3      : std_logic; 
00189 signal dummy_write_state        : std_logic;
00190 signal dummy_write_state_r      : std_logic;
00191 signal pattern_read_state       : std_logic;
00192 signal pattern_read_state_r2    : std_logic;
00193 signal pattern_read_state_r3    : std_logic;
00194 signal dummy_write_flag         : std_logic;
00195 
00196 constant IDLE                    : std_logic_vector(4 downto 0) := "00000";--  5'h00
00197 constant LOAD_MODE_REG_ST        : std_logic_vector(4 downto 0) := "00001";--  5'h01
00198 constant MODE_REGISTER_WAIT      : std_logic_vector(4 downto 0) := "00010";--  5'h02
00199 constant PRECHARGE               : std_logic_vector(4 downto 0) := "00011";--  5'h03
00200 constant PRECHARGE_WAIT          : std_logic_vector(4 downto 0) := "00100";--  5'h04
00201 constant AUTO_REFRESH            : std_logic_vector(4 downto 0) := "00101";--  5'h05
00202 constant AUTO_REFRESH_WAIT       : std_logic_vector(4 downto 0) := "00110";--  5'h06
00203 constant ACTIVE                  : std_logic_vector(4 downto 0) := "00111";--  5'h07
00204 constant ACTIVE_WAIT             : std_logic_vector(4 downto 0) := "01000";--  5'h08
00205 constant FIRST_WRITE             : std_logic_vector(4 downto 0) := "01001";--  5'h09
00206 constant BURST_WRITE             : std_logic_vector(4 downto 0) := "01010";--  5'h0A
00207 constant WRITE_WAIT              : std_logic_vector(4 downto 0) := "01011";--  5'h0B
00208 constant WRITE_READ              : std_logic_vector(4 downto 0) := "01100";--  5'h0C
00209 constant FIRST_READ              : std_logic_vector(4 downto 0) := "01101";--  5'h0D
00210 constant BURST_READ              : std_logic_vector(4 downto 0) := "01110";--  5'h0E
00211 constant READ_WAIT               : std_logic_vector(4 downto 0) := "01111";--  5'h0F
00212 constant READ_WRITE              : std_logic_vector(4 downto 0) := "10000";--  5'h10
00213 
00214 constant INIT_IDLE               : std_logic_vector(4 downto 0) := "00000";--  5'h01
00215 constant INIT_DEEP_MEMORY_ST     : std_logic_vector(4 downto 0) := "00001";--  5'h02
00216 constant INIT_INITCOUNT_200      : std_logic_vector(4 downto 0) := "00010";--  5'h03
00217 constant INIT_INITCOUNT_200_WAIT : std_logic_vector(4 downto 0) := "00011";--  5'h04
00218 constant INIT_DUMMY_READ_CYCLES  : std_logic_vector(4 downto 0) := "00100";--  5'h05
00219 constant INIT_DUMMY_ACTIVE       : std_logic_vector(4 downto 0) := "00101";--  5'h06
00220 constant INIT_DUMMY_ACTIVE_WAIT  : std_logic_vector(4 downto 0) := "00110";--  5'h07
00221 constant INIT_DUMMY_FIRST_READ   : std_logic_vector(4 downto 0) := "00111";--  5'h08
00222 constant INIT_DUMMY_READ         : std_logic_vector(4 downto 0) := "01000";--  5'h09
00223 constant INIT_DUMMY_READ_WAIT    : std_logic_vector(4 downto 0) := "01001";--  5'h0A
00224 constant INIT_DUMMY_WRITE        : std_logic_vector(4 downto 0) := "01010";--  5'h0B
00225 constant INIT_DUMMY_WRITE_READ   : std_logic_vector(4 downto 0) := "01011";--  5'h0C
00226 constant INIT_PATTERN_READ       : std_logic_vector(4 downto 0) := "01100";--  5'h0D
00227 constant INIT_PATTERN_READ_WAIT  : std_logic_vector(4 downto 0) := "01101";--  5'h0E
00228 constant INIT_PRECHARGE          : std_logic_vector(4 downto 0) := "01110";--  5'h0F
00229 constant INIT_PRECHARGE_WAIT     : std_logic_vector(4 downto 0) := "01111";--  5'h10
00230 constant INIT_AUTO_REFRESH       : std_logic_vector(4 downto 0) := "10000";--  5'h11
00231 constant INIT_AUTO_REFRESH_WAIT  : std_logic_vector(4 downto 0) := "10001";--  5'h12
00232 constant INIT_LOAD_MODE_REG_ST   : std_logic_vector(4 downto 0) := "10010";--  5'h13
00233 constant INIT_MODE_REGISTER_WAIT : std_logic_vector(4 downto 0) := "10011";--  5'h14
00234 
00235 signal ctrl_Wdf_RdEn_r          : std_logic; 
00236 signal ctrl_Wdf_RdEn_r1         : std_logic;
00237 signal ctrl_Dqs_Rst_r           : std_logic;  
00238 signal ctrl_Dqs_Rst_r1          : std_logic; 
00239 signal ctrl_WrEn_r              : std_logic;     
00240 signal ctrl_WrEn_r1             : std_logic;    
00241 signal ctrl_RdEn_r              : std_logic;     
00242 signal ctrl_RdEn_r1             : std_logic;    
00243 signal ctrl_Dqs_En_r            : std_logic;   
00244 signal ctrl_Dqs_En_r1           : std_logic;  
00245 
00246 signal dummy_write_pattern_1    : std_logic;
00247 signal dummy_write_pattern_2    : std_logic;
00248 signal ddr_address_r2           : std_logic_vector((row_address - 1) downto 0);
00249 signal ddr_ba_r2                : std_logic_vector((bank_address - 1) downto 0);
00250 signal init_next_state          : std_logic_vector(4 downto 0);       
00251 signal init_state               : std_logic_vector(4 downto 0);            
00252 signal init_state_r2            : std_logic_vector(4 downto 0);         
00253 signal init_state_r3            : std_logic_vector(4 downto 0);
00254 
00255 signal count5                   : std_logic_vector(4 downto 0);
00256 constant cntnext : std_logic_vector(4 downto 0) := "11000";
00257 
00258 
00259 
00260 begin
00261 
00262 
00263 
00264  REGISTERED_VALUE <= '0';
00265 
00266 
00267 CAS_LATENCY_VALUE       <= "0010" when (load_mode_reg(6 downto 4) = "110") else 
00268                             '0' & load_mode_reg(6 downto 4) ;
00269 BURST_LENGTH_VALUE      <= load_mode_reg(2 downto 0);
00270 burst_length            <= burst_cnt(2 downto 0);
00271 command_address         <= af_addr(34 downto 32);
00272 zeroes                  <= (others => '0');
00273 ECC_VALUE               <= ecc_enable;
00274 
00275 
00276 burst_read_state        <= '1' when ((conflict_detect = '0') or (conflict_resolved_r = '1')) and (state = BURST_READ) and (RD = '1') else '0';
00277 first_read_state        <= '1' when ((conflict_detect = '0') or (conflict_resolved_r = '1')) and (state = FIRST_READ) and (RD = '1') else '0';
00278 read_state              <= burst_read_state or first_read_state;
00279 read_write_state        <= write_state or read_state;
00280 burst_write_state       <= '1' when ((conflict_detect = '0') or (conflict_resolved_r = '1')) and (state = BURST_WRITE) and (WR = '1') else '0';
00281 first_write_state       <= '1' when ((conflict_detect = '0') or (conflict_resolved_r = '1')) and (state = FIRST_WRITE) and (WR = '1') else '0';
00282 write_state             <= burst_write_state or first_write_state;
00283    
00284 dummy_write_state       <= '1' when (init_state = INIT_DUMMY_WRITE) else '0';   
00285 dummy_write_pattern_1   <= '1' when ((init_state = INIT_DUMMY_WRITE) or (init_state = INIT_DUMMY_WRITE_READ)) else '0';   
00286 pattern_read_state      <= '1' when (init_state = INIT_PATTERN_READ) else '0';
00287    
00288 process(clk_0)
00289 begin
00290  if(clk_0'event and clk_0 = '1') then
00291   if(rst = '1') then
00292    dummy_write_pattern_2 <= '0';
00293   else
00294    dummy_write_pattern_2 <= dummy_write_pattern_1;
00295   end if;
00296  end if;
00297 end process;
00298 
00299 dummy_write_pattern <= dummy_write_pattern_2 when (REGISTERED_VALUE = '1') else dummy_write_pattern_1;
00300 
00301 -- fifo control signals
00302 
00303 ctrl_af_RdEn <= af_rden;  
00304 
00305 conflict_detect <= af_addr(35) and ctrl_init_done and (not af_empty);
00306    
00307 process(clk_0)
00308 begin
00309  if(clk_0'event and clk_0 = '1') then
00310   if(rst = '1') then
00311         pattern_read_state_r2 <= '0';
00312         pattern_read_state_r3 <= '0';       
00313   else
00314         pattern_read_state_r2 <= pattern_read_state;
00315         pattern_read_state_r3 <= pattern_read_state_r2;
00316   end if;
00317  end if;
00318 end process;
00319 
00320 process(clk_0)
00321 begin
00322  if(clk_0'event and clk_0 = '1') then
00323   if(rst = '1') then
00324    dummy_write_state_r <= '0';
00325   else
00326    dummy_write_state_r <= dummy_write_state;
00327   end if;
00328  end if;
00329 end process;
00330 
00331 --commands
00332 
00333 process(command_address, ctrl_init_done, af_empty)
00334   begin
00335      WR  <= '0';
00336      RD  <= '0';
00337      LMR <= '0';
00338      PRE <= '0';
00339      REF <= '0';
00340      ACT <= '0';
00341      if((ctrl_init_done = '1') and (af_empty = '0')) then
00342         case command_address is
00343                 when "000" => LMR <= '1';
00344                 when "001" => REF <= '1';
00345                 when "010" => PRE <= '1';
00346                 when "011" => ACT <= '1';
00347                 when "100" => WR  <= '1';
00348                 when "101" => RD  <= '1';
00349                 when others => null;
00350         end case;
00351      end if;
00352   end process;
00353 
00354 -- register address outputs
00355 process (clk_0)
00356 begin
00357  if(clk_0'event and clk_0 = '1') then
00358   if(rst = '1') then 
00359      WR_r  <= '0';
00360      RD_r  <= '0';
00361      LMR_r <= '0';
00362      PRE_r <= '0';
00363      REF_r <= '0';
00364      ACT_r <= '0';
00365      af_empty_r <= '0';
00366      LMR_PRE_REF_ACT_cmd_r <= '0';
00367   else
00368      WR_r  <= WR;
00369      RD_r  <= RD;
00370      LMR_r <= LMR;
00371      PRE_r <= PRE;
00372      REF_r <= REF;
00373      ACT_r <= ACT;
00374      LMR_PRE_REF_ACT_cmd_r <= LMR or PRE or REF or ACT;
00375      af_empty_r <= af_empty;
00376   end if;
00377  end if;
00378 end process;
00379    
00380 
00381 -- register address outputs
00382 process (clk_0)
00383 begin
00384  if(clk_0'event and clk_0 = '1') then
00385    if(rst = '1') then
00386      af_addr_r           <= (others => '0');
00387      af_addr_r1          <= (others => '0');
00388      conflict_detect_r   <= '0';
00389      read_write_state_r2 <= '0';
00390      read_write_state_r3 <= '0';
00391      first_read_state_r2 <= '0';
00392      burst_read_state_r2 <= '0';
00393      burst_read_state_r3 <= '0';
00394   else
00395      af_addr_r          <= af_addr;
00396      af_addr_r1         <= af_addr_r;
00397      conflict_detect_r  <= conflict_detect;
00398      read_write_state_r2 <= read_write_state;
00399      read_write_state_r3 <= read_write_state_r2;
00400      first_read_state_r2 <= first_read_state;
00401      burst_read_state_r2 <= burst_read_state;
00402      burst_read_state_r3 <= burst_read_state_r2;
00403   end if;
00404  end if;
00405 end process;
00406 
00407  
00408 process (clk_0)
00409 begin
00410  if(clk_0'event and clk_0 = '1') then
00411    if(rst = '1') then
00412      load_mode_reg         <= load_mode_register((row_address-1) downto 0);
00413   elsif((state = LOAD_MODE_REG_ST or init_state = INIT_LOAD_MODE_REG_ST) and (LMR_r = '1') and (af_addr_r((bank_address+row_address + col_ap_width -1) downto (col_ap_width + row_address))="00")) then
00414      load_mode_reg         <=  af_addr ((row_address-1) downto 0);
00415   end if;
00416  end if;
00417 end process;
00418 
00419 process (clk_0)
00420 begin
00421  if(clk_0'event and clk_0 = '1') then
00422    if(rst = '1') then
00423      ext_mode_reg         <= ext_load_mode_register((row_address-1) downto 0);
00424   elsif((state = LOAD_MODE_REG_ST or init_state = INIT_LOAD_MODE_REG_ST) and (LMR_r = '1') and (af_addr_r((bank_address+row_address + col_ap_width -1) downto (col_ap_width + row_address))= "01")) then
00425      ext_mode_reg         <=  af_addr (row_address-1 downto 0);
00426   end if;
00427  end if;
00428 end process;
00429  
00430 --to initialize memory
00431 process (clk_0)
00432 begin
00433  if(clk_0'event and clk_0 = '1') then
00434     if ((rst = '1') or (init_state = INIT_DEEP_MEMORY_ST)) then
00435         init_memory <= '1';
00436    elsif (init_count_cp = "1010") then
00437         init_memory <= '0';
00438    else
00439         init_memory <= init_memory;
00440   end if;
00441  end if;
00442 end process;
00443       
00444 -- mrd count
00445 process (clk_0)
00446 begin
00447  if(clk_0'event and clk_0 = '1') then
00448     if(rst = '1') then
00449        mrd_count <= '0';
00450    elsif (state = LOAD_MODE_REG_ST) then
00451        mrd_count <= mrd_count_value;
00452    elsif (mrd_count /= '0') then
00453       mrd_count <= '0';
00454    else
00455      mrd_count <= '0';
00456   end if;
00457  end if;
00458 end process;
00459       
00460 -- rp count
00461 process (clk_0)
00462 begin
00463  if(clk_0'event and clk_0 = '1') then
00464     if(rst = '1') then
00465        rp_count(2 downto 0) <= "000";
00466    elsif (state = PRECHARGE) then
00467        rp_count(2 downto 0) <= rp_count_value;
00468    elsif (rp_count(2 downto 0) /= "000") then
00469        rp_count(2 downto 0) <= rp_count(2 downto 0) - 1;
00470    else
00471      rp_count(2 downto 0) <= "000";
00472   end if;
00473  end if;
00474 end process;
00475 
00476 -- rfc count
00477 process (clk_0)
00478 begin
00479  if(clk_0'event and clk_0 = '1') then
00480     if(rst = '1') then
00481        rfc_count(5 downto 0) <= "000000";
00482    elsif (state = AUTO_REFRESH) then
00483        rfc_count(5 downto 0) <= rfc_count_value;
00484    elsif (rfc_count(5 downto 0) /= "000000") then
00485        rfc_count(5 downto 0) <= rfc_count(5 downto 0) - 1;
00486    else
00487      rfc_count(5 downto 0) <= "000000";
00488   end if;
00489  end if;
00490 end process;
00491       
00492 -- rcd count - 20ns
00493 process (clk_0)
00494 begin
00495  if(clk_0'event and clk_0 = '1') then
00496     if(rst = '1') then
00497        rcd_count(2 downto 0) <= "000";
00498    elsif (state = ACTIVE) then
00499        rcd_count(2 downto 0) <= rcd_count_value;
00500    elsif (rcd_count(2 downto 0) /= "000") then
00501        rcd_count(2 downto 0) <= rcd_count(2 downto 0) - 1;
00502    else
00503        rcd_count(2 downto 0) <=  "000";
00504   end if;
00505  end if;
00506 end process;
00507 
00508      
00509 -- ras count - active to precharge
00510 process (clk_0)
00511 begin
00512  if(clk_0'event and clk_0 = '1') then
00513     if(rst = '1') then
00514        ras_count(3 downto 0) <= "0000";
00515    elsif (state = ACTIVE) then
00516        ras_count(3 downto 0) <= ras_count_value;
00517    elsif (ras_count(3 downto 1) = "000") then
00518        if (ras_count(0) /= '0') then
00519               ras_count(0) <= '0';
00520        end if;
00521    else
00522        ras_count(3 downto 0) <= ras_count(3 downto 0) - 1;
00523   end if;
00524  end if;
00525 end process;
00526       
00527 --AL+BL/2+TRTP-2      
00528 -- rtp count - read to precharge
00529 process (clk_0)
00530 begin
00531  if(clk_0'event and clk_0 = '1') then
00532     if(rst = '1') then
00533        rtp_count(3 downto 0) <= "0000";
00534    elsif (read_state = '1') then
00535        rtp_count(2 downto 0) <= trtp_count_value ;
00536    elsif (rtp_count(3 downto 1) = "000") then
00537        if (rtp_count(0) /= '0') then
00538               rtp_count(0) <= '0';
00539        end if;
00540    else
00541        rtp_count(3 downto 0) <= rtp_count(3 downto 0) - 1;
00542   end if;
00543  end if;
00544 end process;
00545 
00546 
00547 
00548 -- WL+BL/2+TWR      
00549 -- wtp count - write to precharge
00550 process (clk_0)
00551 begin
00552  if(clk_0'event and clk_0 = '1') then
00553     if(rst = '1') then
00554        wtp_count(3 downto 0) <= "0000";
00555    elsif (write_state = '1') then
00556        wtp_count(2 downto 0) <= twr_count_value  ;
00557    elsif (wtp_count(3 downto 1) = "000") then
00558        if (wtp_count(0) /= '0') then
00559               wtp_count(0) <= '0';
00560        end if;
00561    else
00562        wtp_count(3 downto 0) <= wtp_count(3 downto 0) - 1;
00563   end if;
00564  end if;
00565 end process;
00566 
00567 
00568       
00569 -- write to read counter 
00570       
00571 process (clk_0)
00572 begin
00573  if(clk_0'event and clk_0 = '1') then
00574     if(rst = '1') then
00575        wr_to_rd_count(3 downto 0) <= "0000";
00576    elsif (write_state = '1') then
00577        wr_to_rd_count(2 downto 0) <= twtr_count_value;
00578    elsif (wr_to_rd_count(3 downto 0) /= "0000") then
00579        wr_to_rd_count(3 downto 0) <= wr_to_rd_count(3 downto 0) - 1;
00580    else
00581      wr_to_rd_count(3 downto 0) <= "0000";
00582   end if;
00583  end if;
00584 end process;
00585 
00586 -- read to write counter
00587 process (clk_0)
00588 begin
00589  if(clk_0'event and clk_0 = '1') then
00590     if(rst = '1') then
00591       rd_to_wr_count(3 downto 0) <= "0000";
00592    elsif (read_state = '1') then
00593       rd_to_wr_count(3 downto 0) <=  registered + burst_cnt + load_mode_reg(6) + load_mode_reg(4);
00594    elsif (rd_to_wr_count(3 downto 0) /= "0000") then
00595       rd_to_wr_count(3 downto 0) <= rd_to_wr_count(3 downto 0) - 1;
00596    else
00597      rd_to_wr_count(3 downto 0) <= "0000";
00598   end if;
00599  end if;
00600 end process;
00601        
00602 
00603 -- auto refresh interval counter in refresh_clk domain
00604 process (refresh_clk)
00605 begin
00606  if(refresh_clk'event and refresh_clk = '1') then
00607    if(rst = '1') then
00608       refi_count <= (others => '0');
00609    elsif (refi_count = max_ref_cnt ) then
00610       refi_count <= (others => '0');
00611    else
00612       refi_count <= refi_count + 1;
00613   end if;
00614  end if;
00615 end process;
00616 
00617  ref_flag <= '1' when ((refi_count = max_ref_cnt) and (done_200us = '1') ) else
00618             '0';
00619 
00620 --200us counter for cke 
00621 process (refresh_clk) 
00622 begin
00623  if(refresh_clk'event and refresh_clk = '1') then
00624   if (rst = '1') then
00625     cke_200us_cnt <= "11011";
00626   elsif (refi_count(max_ref_width-1  downto  0) =  max_ref_cnt) then
00627     cke_200us_cnt  <=  cke_200us_cnt - 1;   
00628   else  
00629     cke_200us_cnt  <= cke_200us_cnt;
00630   end if;
00631  end if;
00632 end process;
00633 
00634 
00635 -- refresh detect in 266 MHz clock
00636 process (clk_0)
00637 begin
00638  if(clk_0'event and clk_0 = '1') then
00639     if(rst = '1') then
00640       ref_flag_266   <= '0';
00641       ref_flag_266_r <= '0';
00642       done_200us <= '0';
00643    else
00644       ref_flag_266   <= ref_flag;
00645       ref_flag_266_r <= ref_flag_266;
00646       if (done_200us = '0' and (cke_200us_cnt = "00000")) then
00647         done_200us <= '1';
00648       end if;
00649   end if;
00650  end if;
00651 end process;
00652       
00653 --refresh flag detect
00654 --auto_ref high indicates auto_refresh requirement
00655 --auto_ref is held high until auto refresh command is issued.
00656 process(clk_0)
00657 begin
00658  if(clk_0'event and clk_0 = '1') then
00659     if(rst = '1') then
00660        auto_ref <= '0';
00661     elsif (ref_flag_266 = '1' and ref_flag_266_r = '0') then
00662        auto_ref <= '1';
00663     elsif ((state = AUTO_REFRESH) or (init_state = INIT_AUTO_REFRESH)) then
00664        auto_ref <= '0';
00665     else 
00666        auto_ref <= auto_ref;
00667   end if;
00668  end if;
00669 end process;
00670         
00671 -- 200 clocks counter - count value : C8
00672 -- required for initialization
00673 process (clk_0)
00674 begin
00675  if(clk_0'event and clk_0 = '1') then
00676     if(rst = '1') then
00677        count_200_cycle(7 downto 0) <= "00000000";
00678    elsif (init_state = INIT_INITCOUNT_200) then
00679        count_200_cycle(7 downto 0) <= "11001000";
00680    elsif (count_200_cycle(7 downto 0) /= "00000000") then
00681        count_200_cycle(7 downto 0) <= count_200_cycle(7 downto 0) - 1;
00682    else
00683        count_200_cycle(7 downto 0) <= "00000000";
00684   end if;
00685  end if;
00686 end process;
00687 
00688 process (clk_0)
00689 begin
00690  if(clk_0'event and clk_0 = '1') then
00691     if(rst = '1') then
00692        count_200cycle_done_r<= '0';
00693    elsif ((init_memory = '1') and (count_200_cycle = "00000000")) then
00694        count_200cycle_done_r<= '1';
00695    else
00696        count_200cycle_done_r<= '0';
00697   end if;
00698  end if;
00699 end process;
00700       
00701 
00702 process (clk_0)
00703 begin
00704  if(clk_0'event and clk_0 = '1') then
00705     if(rst = '1') then
00706       init_done <= '0';
00707    elsif ((Phy_Mode = '1') and (comp_done ='1') and (count5 = "10100")) then
00708       init_done <= '1';
00709    else
00710       init_done <= init_done;
00711   end if;
00712  end if;
00713 end process;
00714                              
00715  ctrl_init_done      <= init_done;
00716                             
00717  burst_cnt           <= "0010" when (BURST_LENGTH_VALUE = "010") else
00718                        "0100" when (BURST_LENGTH_VALUE = "011") else
00719                        "0001";
00720  burst_cnt_by2       <= "001" when (BURST_LENGTH_VALUE = "010") else
00721                        "010" when (BURST_LENGTH_VALUE = "011") else
00722                        "000";
00723                                     
00724 process (clk_0)
00725 begin
00726  if(clk_0'event and clk_0 = '1') then
00727    if ((rst = '1')or (init_state = INIT_DEEP_MEMORY_ST)) then
00728      init_count(3 downto 0) <= "0000";
00729   elsif (init_memory = '1') then
00730      if (init_state = INIT_LOAD_MODE_REG_ST or init_state = INIT_PRECHARGE or init_state = INIT_AUTO_REFRESH or 
00731          init_state = INIT_DUMMY_READ_CYCLES or init_state = INIT_INITCOUNT_200 or init_state = INIT_DEEP_MEMORY_ST) then
00732         init_count(3 downto 0) <= init_count(3 downto 0) + 1;
00733      elsif(init_count = "1010" ) then
00734         init_count(3 downto 0) <= "0000";   
00735      else init_count(3 downto 0) <= init_count(3 downto 0);
00736      end if;
00737   end if;
00738  end if;
00739 end process;
00740 
00741 process (clk_0)
00742 begin
00743  if(clk_0'event and clk_0 = '1') then
00744     if ((rst = '1')or (init_state = INIT_DEEP_MEMORY_ST)) then
00745       init_count_cp(3 downto 0) <= "0000";
00746    elsif (init_memory = '1') then
00747       if (init_state = INIT_LOAD_MODE_REG_ST or init_state = INIT_PRECHARGE or init_state = INIT_AUTO_REFRESH or 
00748           init_state = INIT_DUMMY_READ_CYCLES or init_state = INIT_INITCOUNT_200 or init_state = INIT_DEEP_MEMORY_ST) then
00749          init_count_cp(3 downto 0) <= init_count_cp(3 downto 0) + 1;
00750       elsif(init_count_cp = "1010" ) then
00751          init_count_cp(3 downto 0) <= "0000";   
00752       else init_count_cp(3 downto 0) <= init_count_cp(3 downto 0);
00753       end if;
00754   end if;
00755  end if;
00756 end process;
00757    
00758 process (clk_0)
00759 begin
00760  if(clk_0'event and clk_0 = '1') then
00761     if(rst = '1') then
00762         chip_cnt <= "00";
00763    elsif ( init_state = INIT_DEEP_MEMORY_ST) then
00764       chip_cnt <= chip_cnt + "01";
00765    else
00766       chip_cnt <= chip_cnt;
00767   end if;
00768  end if;
00769 end process;
00770 
00771    
00772 
00773 -- write burst count
00774 process (clk_0)
00775 begin
00776  if(clk_0'event and clk_0 = '1') then
00777     if(rst = '1') then
00778        wrburst_cnt(2 downto 0) <= "000";
00779    elsif (write_state = '1' or dummy_write_state = '1') then
00780        wrburst_cnt(2 downto 0) <= burst_cnt(2 downto 0);
00781    elsif (wrburst_cnt(2 downto 0) /= "000") then
00782        wrburst_cnt(2 downto 0) <= wrburst_cnt(2 downto 0) - 1;
00783    else wrburst_cnt(2 downto 0) <= "000";
00784   end if;
00785  end if;
00786 end process;
00787 
00788 -- read burst count for state machine 
00789 process (clk_0)
00790 begin
00791  if(clk_0'event and clk_0 = '1') then
00792     if(rst = '1') then
00793        read_burst_cnt(2 downto 0) <= "000";
00794    elsif (read_state = '1') then
00795        read_burst_cnt(2 downto 0) <= burst_cnt(2 downto 0);
00796    elsif (read_burst_cnt(2 downto 0) /= "000") then
00797        read_burst_cnt(2 downto 0) <= read_burst_cnt(2 downto 0) - 1;
00798    else read_burst_cnt(2 downto 0) <= "000";
00799   end if;
00800  end if;
00801 end process;
00802 
00803 -- count to generate write enable to the data path
00804 process (clk_0)
00805 begin
00806  if(clk_0'event and clk_0 = '1') then
00807     if(rst = '1') then
00808        ctrl_WrEn_cnt(2 downto 0) <= "000";
00809    elsif ((wdf_rden_r = '1') or (dummy_write_state_r = '1')) then
00810        ctrl_WrEn_cnt(2 downto 0) <= burst_cnt(2 downto 0);
00811    elsif (ctrl_WrEn_cnt(2 downto 0) /= "000") then
00812        ctrl_WrEn_cnt(2 downto 0) <= ctrl_WrEn_cnt(2 downto 0) -1;
00813    else 
00814        ctrl_WrEn_cnt(2 downto 0) <= "000";
00815   end if;
00816  end if;
00817 end process;
00818 
00819 --write enable to data path
00820 process (ctrl_WrEn_cnt) 
00821 begin
00822      if (ctrl_WrEn_cnt(2 downto 0) /= "000") then
00823         ctrl_WrEn_r <= '1';
00824      else
00825         ctrl_WrEn_r <= '0';
00826      end if;
00827 end process;
00828     
00829 process(clk_0)
00830 begin
00831  if(clk_0'event and clk_0 = '1') then
00832     if(rst = '1') then
00833         ctrl_WrEn_r1 <= '0';
00834     else
00835         ctrl_WrEn_r1 <= ctrl_WrEn_r;
00836     end if;
00837  end if;
00838 end process;
00839 
00840 ctrl_WrEn <= ctrl_WrEn_r1 when (REGISTERED_VALUE = '1') else
00841              ctrl_WrEn_r;
00842 
00843 
00844 -- DQS reset to data path
00845 process (clk_0)
00846 begin
00847  if(clk_0'event and clk_0 = '1') then
00848     if(rst = '1') then
00849       ctrl_Dqs_Rst_r <= '0';
00850    elsif (first_write_state = '1' or init_state = INIT_DUMMY_WRITE) then
00851       ctrl_Dqs_Rst_r <= '1';
00852    else 
00853       ctrl_Dqs_Rst_r <= '0';
00854   end if;
00855  end if;
00856 end process;
00857 
00858 process(clk_0)
00859 begin
00860  if(clk_0'event and clk_0 = '1') then
00861     if(rst = '1') then
00862         ctrl_Dqs_Rst_r1 <= '0';
00863     else
00864         ctrl_Dqs_Rst_r1 <= ctrl_Dqs_Rst_r;
00865     end if;
00866  end if;
00867 end process;
00868 
00869 ctrl_Dqs_Rst <= ctrl_Dqs_Rst_r1 when (REGISTERED_VALUE = '1') else
00870                 ctrl_Dqs_Rst_r;
00871 
00872 
00873 -- DQS enable to data path
00874 process (clk_0)
00875 begin
00876  if(clk_0'event and clk_0 = '1') then
00877     if(rst = '1') then
00878       ctrl_Dqs_En_r <= '0';
00879    elsif ((write_state = '1') or (wrburst_cnt /= "000") or (dummy_write_state = '1')) then
00880       ctrl_Dqs_En_r <= '1';
00881    else 
00882       ctrl_Dqs_En_r <= '0';
00883   end if;
00884  end if;
00885 end process;
00886 
00887 process(clk_0)
00888 begin
00889  if(clk_0'event and clk_0 = '1') then
00890     if(rst = '1') then
00891         ctrl_Dqs_En_r1 <= '0';
00892     else
00893         ctrl_Dqs_En_r1 <= ctrl_Dqs_En_r;
00894     end if;
00895  end if;
00896 end process;
00897 
00898 ctrl_Dqs_En <= ctrl_Dqs_En_r1 when (REGISTERED_VALUE = '1') else
00899                ctrl_Dqs_En_r;
00900                
00901 
00902 -- cas count
00903 process (clk_0)
00904 begin
00905  if(clk_0'event and clk_0 = '1') then
00906     if(rst = '1') then
00907       cas_count(2 downto 0) <= "000";
00908    elsif ((init_state = INIT_DUMMY_FIRST_READ)) then
00909       cas_count(2 downto 0) <= CAS_LATENCY_VALUE(2 downto 0) + registered;
00910    elsif (cas_count(2 downto 0) /= "000") then
00911       cas_count(2 downto 0) <= cas_count(2 downto 0) - 1;
00912    else cas_count(2 downto 0) <= "000";
00913   end if;
00914  end if;
00915 end process;
00916 
00917 --dummy_read enable
00918 process (clk_0)
00919 begin
00920  if(clk_0'event and clk_0 = '1') then
00921     if(rst = '1') then
00922       dummy_read_en <= '0';
00923    elsif (init_state = INIT_DUMMY_READ) then
00924       dummy_read_en <= '1';
00925    elsif (phy_Dly_Slct_Done = '1') then
00926       dummy_read_en <= '0';
00927    else dummy_read_en <= dummy_read_en;
00928   end if;
00929  end if;
00930 end process;
00931 
00932   
00933 -- ctrl_Dummyread_Start signal generation to the data path module
00934 process (clk_0)
00935 begin
00936  if(clk_0'event and clk_0 = '1') then
00937     if(rst = '1') then
00938 
00939        ctrl_Dummyread_Start_r1 <= '0';
00940    elsif ((dummy_read_en = '1') and (cas_count = "000")) then
00941        ctrl_Dummyread_Start_r1 <= '1';
00942    elsif (phy_Dly_Slct_Done = '1') then
00943        ctrl_Dummyread_Start_r1 <= '0';
00944    else ctrl_Dummyread_Start_r1 <= ctrl_Dummyread_Start_r1;
00945   end if;
00946  end if;
00947 end process;
00948  
00949 -- register ctrl_Dummyread_Start signal
00950 process (clk_0)
00951 begin
00952  if(clk_0'event and clk_0 = '1') then
00953     if(rst = '1') then
00954       ctrl_Dummyread_Start_r2 <= '0'; 
00955       ctrl_Dummyread_Start_r3 <= '0';
00956       ctrl_Dummyread_Start_r4 <= '0';
00957       ctrl_Dummyread_Start <= '0';
00958    else
00959       ctrl_Dummyread_Start_r2 <=  ctrl_Dummyread_Start_r1;
00960       ctrl_Dummyread_Start_r3 <=  ctrl_Dummyread_Start_r2;
00961       ctrl_Dummyread_Start_r4 <=  ctrl_Dummyread_Start_r3;
00962       ctrl_Dummyread_Start <=  ctrl_Dummyread_Start_r4;
00963   end if;
00964  end if;
00965 end process;
00966          
00967 -- read_wait/write_wait to idle count
00968 -- the state machine waits for 15 clock cycles in the write wait state for any wr/rd commands
00969 -- to be issued. If no commands are issued in 15 clock cycles, the statemachine issues
00970 --  enters the idle state and stays in the idle state until an auto refresh is required.
00971 
00972 process (clk_0)
00973 begin
00974  if(clk_0'event and clk_0 = '1') then
00975     if(rst = '1') then
00976        idle_cnt(3 downto 0) <= "0000";
00977    elsif (read_write_state = '1') then
00978        idle_cnt(3 downto 0) <= "1111" ;
00979    elsif (idle_cnt(3 downto 0) /= "0000") then
00980        idle_cnt(3 downto 0) <= idle_cnt(3 downto 0) - 1;
00981    else idle_cnt(3 downto 0) <= "0000";
00982   end if;
00983  end if;
00984 end process;
00985 
00986 
00987 
00988 process (clk_0)
00989 begin
00990  if(clk_0'event and clk_0 = '1') then
00991     if(rst = '1') then
00992        cas_check_count(3 downto 0) <= "0000";
00993    elsif (first_read_state_r2 = '1' or pattern_read_state_r2 = '1')  then
00994           cas_check_count(3 downto 0) <= (CAS_LATENCY_VALUE - 1);
00995    elsif (cas_check_count(3 downto 0) /= "0000") then
00996        cas_check_count(3 downto 0) <= cas_check_count(3 downto 0) - 1;
00997    else
00998      cas_check_count(3 downto 0) <= "0000";
00999   end if;
01000  end if;
01001 end process;
01002 
01003 process (clk_0)
01004 begin
01005  if(clk_0'event and clk_0 = '1') then
01006     if (rst = '1') then
01007       rdburst_cnt(2 downto 0) <= "000";
01008       ctrl_RdEn_r <= '0';
01009    elsif ((cas_check_count = "0001") and (burst_read_state_r3 = '0')) then
01010       rdburst_cnt(2 downto 0) <= burst_cnt(2 downto 0);
01011       ctrl_RdEn_r <= '1';
01012    elsif(burst_read_state_r3 = '1' or pattern_read_state_r3 = '1') then
01013       if(burst_cnt = "0100") then
01014         rdburst_cnt(2 downto 0) <= CAS_LATENCY_VALUE(2 downto 0) + burst_cnt_by2;--burst_cnt(2 downto 0)/2;--"010"; --;
01015       elsif (burst_cnt = "010") then
01016         rdburst_cnt(2 downto 0) <= CAS_LATENCY_VALUE(2 downto 0);
01017       else     
01018         rdburst_cnt(2 downto 0) <= CAS_LATENCY_VALUE(2 downto 0) - burst_cnt(2 downto 0);
01019       end if;
01020           if(burst_read_state_r3 = '1') then
01021                 ctrl_RdEn_r <= '1';
01022           end if;
01023    elsif (rdburst_cnt(2 downto 0) /= "000") then
01024       rdburst_cnt(2 downto 0) <= rdburst_cnt(2 downto 0) - '1';
01025       if(rdburst_cnt = "001") then
01026         ctrl_RdEn_r <= '0';
01027       end if;
01028    else
01029      rdburst_cnt(2 downto 0) <= "000";
01030   end if;
01031  end if;
01032 end process;
01033 
01034 process(clk_0)
01035 begin
01036  if(clk_0'event and clk_0 = '1') then
01037     if (rst = '1') then
01038         ctrl_RdEn_r1 <= '0';
01039     else
01040         ctrl_RdEn_r1 <= ctrl_RdEn_r;
01041     end if;
01042  end if;
01043 end process;
01044 
01045 ctrl_RdEn <= ctrl_RdEn_r1 when (REGISTERED_VALUE = '1') else
01046              ctrl_RdEn_r;
01047 
01048 -- write address FIFO read enable signals
01049 
01050 af_rden <= '1' when ((read_write_state = '1') or ((state = MODE_REGISTER_WAIT) and LMR_r = '1' and (mrd_count = '0')) or 
01051                      ((state = PRECHARGE )and PRE_r = '1') or ((state = AUTO_REFRESH) and REF_r = '1')
01052                      or ((state = ACTIVE )and ACT_r = '1')) else '0';
01053    
01054 
01055 
01056 -- write data fifo read enable
01057 process (clk_0)
01058 begin
01059  if(clk_0'event and clk_0 = '1') then
01060     if (rst = '1')  then
01061        wdf_rden_r  <= '0';
01062    elsif (write_state = '1') then -- place holder for burst_write
01063        wdf_rden_r  <= '1';
01064    else 
01065      wdf_rden_r  <= '0';
01066   end if;
01067  end if;
01068 end process;
01069 
01070 
01071 
01072  
01073 process (clk_0)
01074 begin
01075  if(clk_0'event and clk_0 = '1') then
01076     if (rst = '1') then
01077        wdf_rden_r2 <= '0';
01078        wdf_rden_r3 <= '0';
01079        wdf_rden_r4 <= '0';
01080    else 
01081        wdf_rden_r2 <= wdf_rden_r;
01082        wdf_rden_r3 <= wdf_rden_r2;
01083        wdf_rden_r4 <= wdf_rden_r3;
01084   end if;
01085  end if;
01086 end process;
01087    
01088 
01089 
01090 -- Read enable to the data fifo
01091 
01092 process (burst_cnt, wdf_rden_r, wdf_rden_r2, wdf_rden_r3, wdf_rden_r4) 
01093 begin
01094    if (burst_cnt = "001") then
01095        ctrl_Wdf_RdEn_r<= (wdf_rden_r ) ;   
01096    elsif (burst_cnt = "010") then
01097        ctrl_Wdf_RdEn_r<= (wdf_rden_r or wdf_rden_r2) ;
01098    elsif (burst_cnt = "100") then
01099        ctrl_Wdf_RdEn_r<= (wdf_rden_r or wdf_rden_r2 or wdf_rden_r3 or wdf_rden_r4) ;
01100    else 
01101        ctrl_Wdf_RdEn_r<= '0';
01102    end if;
01103 end process;
01104 
01105 process (clk_0)
01106 begin
01107  if(clk_0'event and clk_0 = '1') then
01108    if(rst = '1') then
01109         ctrl_Wdf_RdEn_r1 <= '0';
01110    else
01111         ctrl_Wdf_RdEn_r1 <= ctrl_Wdf_RdEn_r;
01112    end if;
01113  end if;
01114 end process;
01115 
01116 ctrl_Wdf_RdEn <= ctrl_Wdf_RdEn_r1 when (REGISTERED_VALUE = '1') else
01117                  ctrl_Wdf_RdEn_r;
01118 
01119 
01120 
01121 process(clk_0)                                              
01122 begin                                                       
01123  if(clk_0'event and clk_0 = '1') then                       
01124   if(rst = '1') then                                        
01125         dummy_write_flag <= '0';                              
01126   else
01127         dummy_write_flag <= phy_Dly_Slct_Done and not(comp_done);                              
01128   end if;                                                   
01129  end if;                                                    
01130 end process;                                                
01131 
01132 process (clk_0)
01133 begin
01134  if(clk_0'event and clk_0 = '1') then
01135    if(rst = '1') then
01136       state <= IDLE;
01137   else
01138      state <= next_state;
01139   end if;
01140  end if;
01141 end process;
01142 
01143 process (clk_0)
01144 begin
01145  if(clk_0'event and clk_0 = '1') then
01146    if(rst = '1') then
01147       init_state <= INIT_IDLE;
01148   else
01149      init_state <= init_next_state;
01150   end if;
01151  end if;
01152 end process;
01153           
01154 process (clk_0)
01155 begin
01156  if(clk_0'event and clk_0 = '1') then
01157    if(rst = '1') then
01158       count5 <= (others => '0');
01159    else
01160      case init_state is
01161         when INIT_PRECHARGE_WAIT | INIT_MODE_REGISTER_WAIT | INIT_AUTO_REFRESH_WAIT 
01162         | INIT_DUMMY_WRITE_READ | INIT_PATTERN_READ_WAIT | INIT_DUMMY_READ_WAIT | INIT_DUMMY_ACTIVE_WAIT  =>
01163                 count5 <= count5 + '1';
01164 
01165         when others =>
01166                 count5 <= (others => '0');
01167      end case;
01168    end if;
01169  end if;
01170 end process;
01171 
01172 -- Initialization state machine  
01173 process (auto_ref, chip_cnt, count_200cycle_done_r, done_200us, 
01174          init_count, init_memory, phy_Dly_Slct_Done, init_state, 
01175          burst_cnt, comp_done, dummy_write_flag, REF_r, count5)
01176 begin
01177 
01178    init_next_state <= init_state;
01179    case init_state is
01180         when INIT_IDLE =>
01181         if (init_memory = '1' and done_200us = '1') then
01182            case init_count is -- synthesis parallel_case full_case
01183              when "0000" => init_next_state <= INIT_INITCOUNT_200;
01184              when "0001" => init_next_state <= INIT_PRECHARGE;
01185              when "0010" => init_next_state <= INIT_LOAD_MODE_REG_ST;
01186              when "0011" => init_next_state <= INIT_LOAD_MODE_REG_ST;
01187              when "0100" => init_next_state <= INIT_INITCOUNT_200;
01188              when "0101" => init_next_state <= INIT_PRECHARGE;        
01189              when "0110" => init_next_state <= INIT_AUTO_REFRESH;     
01190              when "0111" => init_next_state <= INIT_AUTO_REFRESH;     
01191              when "1000" => init_next_state <= INIT_LOAD_MODE_REG_ST; 
01192              when "1001" =>
01193                 if( (chip_cnt < no_of_cs-1)) then
01194                   init_next_state <= INIT_DEEP_MEMORY_ST;
01195                 elsif ((Phy_Mode = '1'  and count_200cycle_done_r = '1')) then
01196                   init_next_state <= INIT_DUMMY_READ_CYCLES;
01197                 else
01198                   init_next_state <= INIT_IDLE;
01199                 end if;
01200              when "1010" =>
01201                 if (phy_Dly_Slct_Done = '1') then
01202                    init_next_state <= INIT_IDLE;
01203                 end if;
01204              when others => init_next_state <= INIT_IDLE;
01205 
01206            end case; -- case(init_count )
01207         end if;
01208 
01209       when INIT_DEEP_MEMORY_ST =>  init_next_state <= INIT_IDLE;
01210 
01211       when INIT_INITCOUNT_200 => init_next_state <= INIT_INITCOUNT_200_WAIT;
01212 
01213       when INIT_INITCOUNT_200_WAIT =>
01214         if (count_200cycle_done_r = '1') then
01215           init_next_state <= INIT_IDLE;
01216         else
01217           init_next_state <= INIT_INITCOUNT_200_WAIT;
01218         end if;
01219 
01220       when INIT_DUMMY_READ_CYCLES => init_next_state <= INIT_DUMMY_ACTIVE;
01221 
01222 
01223       when INIT_DUMMY_ACTIVE  =>     init_next_state <= INIT_DUMMY_ACTIVE_WAIT;
01224 
01225 
01226       when INIT_DUMMY_ACTIVE_WAIT =>
01227         if (count5 = cntnext) then
01228           if(dummy_write_flag = '1') then
01229                 init_next_state <= INIT_DUMMY_WRITE;
01230           else
01231                 init_next_state <= INIT_DUMMY_FIRST_READ;
01232           end if;
01233         else
01234           init_next_state <= INIT_DUMMY_ACTIVE_WAIT;
01235         end if;
01236 
01237       when INIT_DUMMY_FIRST_READ  =>
01238                  init_next_state <= INIT_DUMMY_READ_WAIT;
01239 
01240       when INIT_DUMMY_READ =>
01241                 if((burst_cnt = "001") and (phy_Dly_Slct_Done = '0')) then
01242                         init_next_state <= INIT_DUMMY_READ;
01243                 else
01244                         init_next_state <= INIT_DUMMY_READ_WAIT;
01245                 end if;
01246 
01247       when INIT_DUMMY_READ_WAIT =>
01248         if (phy_Dly_Slct_Done = '1') then
01249           if(count5 = cntnext) then
01250             init_next_state <= INIT_PRECHARGE;
01251           else
01252             init_next_state <= INIT_DUMMY_READ_WAIT;
01253           end if;
01254         else
01255           init_next_state <= INIT_DUMMY_READ;
01256         end if;
01257 
01258      when INIT_DUMMY_WRITE =>
01259         init_next_state <= INIT_DUMMY_WRITE_READ;
01260 
01261      when INIT_DUMMY_WRITE_READ =>
01262         if (count5 = cntnext) then
01263             init_next_state <= INIT_PATTERN_READ;
01264         else
01265             init_next_state <= INIT_DUMMY_WRITE_READ;
01266         end if;
01267 
01268       when INIT_PATTERN_READ =>
01269                 init_next_state <= INIT_PATTERN_READ_WAIT;
01270 
01271       when INIT_PATTERN_READ_WAIT =>
01272         if(comp_done = '1') then
01273               init_next_state <= INIT_PRECHARGE;
01274         else
01275               init_next_state <= INIT_PATTERN_READ_WAIT;
01276         end if;
01277 
01278 
01279       when INIT_PRECHARGE  => init_next_state <= INIT_PRECHARGE_WAIT;
01280 
01281 
01282       when INIT_PRECHARGE_WAIT =>
01283         if (count5 = cntnext) then
01284            if ((auto_ref or REF_r) = '1') then
01285               init_next_state <= INIT_AUTO_REFRESH;
01286            else
01287               init_next_state <= INIT_IDLE;
01288            end if;
01289         else
01290            init_next_state <= INIT_PRECHARGE_WAIT;
01291         end if;
01292 
01293      when INIT_LOAD_MODE_REG_ST  => init_next_state <= INIT_MODE_REGISTER_WAIT;
01294 
01295 
01296      when INIT_MODE_REGISTER_WAIT =>
01297         if (count5 = cntnext) then
01298           init_next_state <= INIT_IDLE;
01299         else
01300           init_next_state <= INIT_MODE_REGISTER_WAIT;
01301         end if;
01302 
01303      when INIT_AUTO_REFRESH => init_next_state <= INIT_AUTO_REFRESH_WAIT;
01304 
01305      when INIT_AUTO_REFRESH_WAIT =>
01306         if ( (count5 = cntnext) and (phy_Dly_Slct_Done = '1') ) then
01307            init_next_state <= INIT_DUMMY_ACTIVE;
01308         elsif (count5 = cntnext) then
01309            init_next_state <= INIT_IDLE;
01310         else
01311            init_next_state <= INIT_AUTO_REFRESH_WAIT;
01312         end if;
01313 
01314     when others => init_next_state <= INIT_IDLE;
01315 
01316    end case;
01317  end process;
01318 
01319 --Main control state machine
01320 process (ACT_r, LMR_PRE_REF_ACT_cmd_r, LMR_r, RD                        
01321          , RD_r, REF_r, WR, WR_r, auto_ref
01322          , conflict_detect, conflict_detect_r
01323          , conflict_resolved_r, idle_cnt, mrd_count, ras_count, rcd_count
01324          , rd_to_wr_count, read_burst_cnt, rfc_count, rp_count
01325          , rtp_count, state, wr_to_rd_count, wrburst_cnt
01326          , wtp_count,burst_cnt, init_done, af_empty_r) 
01327 begin
01328           
01329    next_state <= state;
01330    case state is 
01331         when IDLE =>
01332         if ((conflict_detect_r = '1' or LMR_PRE_REF_ACT_cmd_r = '1' or auto_ref = '1') and ras_count = "0000" and init_done = '1') then 
01333            next_state <= PRECHARGE;                        
01334         elsif ((WR_r= '1'  or RD_r= '1') and (ras_count = "0000")) then
01335            next_state <= ACTIVE;           
01336         end if;
01337 
01338         when LOAD_MODE_REG_ST  => next_state <= MODE_REGISTER_WAIT;
01339 
01340         when MODE_REGISTER_WAIT =>
01341         if (mrd_count = '0') then
01342           next_state <= IDLE;
01343         else
01344           next_state <= MODE_REGISTER_WAIT;
01345         end if;
01346 
01347         when PRECHARGE  => next_state <= PRECHARGE_WAIT;
01348 
01349                    
01350         when PRECHARGE_WAIT =>
01351         if (rp_count = "000") then
01352            if ((auto_ref or REF_r) = '1') then
01353               next_state <= AUTO_REFRESH;
01354            elsif (LMR_r = '1') then
01355               next_state <= LOAD_MODE_REG_ST;
01356            elsif ((conflict_detect_r or ACT_r) = '1') then
01357               next_state <= ACTIVE;
01358            else  
01359               next_state <= IDLE;
01360            end if;
01361         else 
01362            next_state <= PRECHARGE_WAIT; 
01363         end if;
01364 
01365         when AUTO_REFRESH => next_state <= AUTO_REFRESH_WAIT;
01366 
01367         when AUTO_REFRESH_WAIT =>
01368         if ( (rfc_count = "00001") and (conflict_detect_r = '1') ) then
01369            next_state <= ACTIVE;
01370         elsif (rfc_count = "00001") then
01371            next_state <= IDLE;
01372         else
01373            next_state <= AUTO_REFRESH_WAIT;
01374         end if;
01375                            
01376         when ACTIVE  => next_state <= ACTIVE_WAIT;
01377 
01378                            
01379         when ACTIVE_WAIT  =>
01380         if (rcd_count = "000") then
01381            if(WR = '1') then
01382              next_state <= FIRST_WRITE;
01383            elsif (RD = '1') then
01384              next_state <= FIRST_READ;
01385            else 
01386              next_state <= IDLE;
01387            end if;
01388         else
01389           next_state <= ACTIVE_WAIT;
01390         end if;
01391                            
01392         when FIRST_WRITE  =>
01393               if((((conflict_detect = '1') and (conflict_resolved_r ='0')) or (auto_ref = '1')) or RD = '1') then
01394                  next_state <= WRITE_WAIT;
01395               elsif((burst_cnt = "001") and (WR = '1')) then
01396                   next_state <= BURST_WRITE;
01397               else
01398                   next_state <= WRITE_WAIT;
01399               end if;
01400      
01401         when BURST_WRITE =>
01402               if((((conflict_detect = '1') and (conflict_resolved_r = '0')) or (auto_ref = '1')) or (RD = '1')) then
01403                  next_state <= WRITE_WAIT;
01404               elsif((burst_cnt = "001") and (WR = '1')) then
01405                   next_state <= BURST_WRITE;
01406               else
01407                   next_state <= WRITE_WAIT;
01408               end if;
01409      
01410         when WRITE_WAIT =>
01411         if (((conflict_detect = '1') and (conflict_resolved_r = '0')) or (auto_ref = '1')) then
01412            if ((wtp_count = "0000") and (ras_count = "0000")) then
01413              next_state <= PRECHARGE;
01414            else   
01415              next_state <= WRITE_WAIT;
01416            end if;
01417         elsif (RD = '1') then
01418            next_state <= WRITE_READ;
01419         elsif ((WR ='1') and (wrburst_cnt = "010")) then
01420            next_state <= BURST_WRITE;
01421         elsif((WR = '1') and (wrburst_cnt = "000")) then --added to improve the efficiency (June 21, 2006)
01422            next_state <= FIRST_WRITE;
01423         elsif (idle_cnt = "0000") then
01424            next_state <= PRECHARGE;    
01425         else
01426            next_state <= WRITE_WAIT;
01427         end if;
01428                             
01429         when WRITE_READ =>
01430         if (wr_to_rd_count = "0000") then
01431            next_state <= FIRST_READ;
01432         else
01433            next_state <= WRITE_READ;
01434         end if;
01435      
01436         when FIRST_READ   =>
01437               if((((conflict_detect = '1') and (conflict_resolved_r = '0')) or (auto_ref = '1')) or (WR = '1')) then
01438                  next_state <= READ_WAIT;
01439               elsif((burst_cnt = "001") and (RD = '1')) then
01440                   next_state <= BURST_READ;
01441               else
01442                   next_state <= READ_WAIT;
01443               end if;
01444 
01445         when BURST_READ  =>
01446               if((((conflict_detect = '1') and (conflict_resolved_r = '0'))or (auto_ref = '1')) or (WR = '1')) then
01447                  next_state <= READ_WAIT;
01448               elsif((burst_cnt = "001") and (RD = '1')) then
01449                   next_state <= BURST_READ;
01450               else
01451                   next_state <= READ_WAIT;
01452               end if;
01453 
01454         when READ_WAIT  =>
01455         if (((conflict_detect = '1') and (conflict_resolved_r = '0')) or (auto_ref = '1')) then
01456            if(rtp_count = "0000" and ras_count = "0000") then
01457              next_state <= PRECHARGE;
01458            else
01459              next_state <= READ_WAIT;  
01460            end if;
01461         elsif (WR = '1') then
01462            next_state <= READ_WRITE;
01463         elsif ((RD = '1') and (read_burst_cnt <= "010")) then
01464            if(af_empty_r = '1') then
01465              next_state <= FIRST_READ;
01466            else
01467              next_state <= BURST_READ;
01468            end if;
01469         elsif (idle_cnt = "0000") then
01470            next_state <= PRECHARGE;  
01471         else
01472            next_state <= READ_WAIT;
01473         end if;
01474 
01475                            
01476         when READ_WRITE  =>
01477         if (rd_to_wr_count = "0000") then
01478            next_state <= FIRST_WRITE;
01479         else
01480            next_state <= READ_WRITE;
01481         end if;
01482      
01483         when others => next_state <= IDLE;
01484 
01485    end case;
01486 end process;    
01487 
01488 
01489 
01490 --register command outputs
01491 process (clk_0)
01492 begin
01493  if(clk_0'event and clk_0 = '1') then
01494     if(rst = '1') then
01495       state_r2 <= "00000";
01496       state_r3 <= "00000";
01497    else
01498       state_r2 <= state;
01499       state_r3 <= state_r2;
01500   end if;
01501  end if;
01502 end process;
01503 
01504 process (clk_0)
01505 begin
01506  if(clk_0'event and clk_0 = '1') then
01507     if(rst = '1') then
01508       init_state_r2 <= "00000";
01509       init_state_r3 <= "00000";
01510    else
01511       init_state_r2 <= init_state;
01512       init_state_r3 <= init_state_r2;
01513   end if;
01514  end if;
01515 end process;
01516 
01517 
01518 -- commands to the memory
01519 process (clk_0)
01520 begin
01521  if(clk_0'event and clk_0 = '1') then
01522     if(rst = '1') then
01523       ddr_ras_r <= '1';
01524    elsif ((state = LOAD_MODE_REG_ST) or (state = PRECHARGE) or (state = ACTIVE) or (state = AUTO_REFRESH)
01525         or (init_state = INIT_LOAD_MODE_REG_ST) or (init_state = INIT_PRECHARGE) or (init_state = INIT_AUTO_REFRESH) 
01526         or (init_state = INIT_DUMMY_ACTIVE)) then
01527       ddr_ras_r <= '0';
01528    else ddr_ras_r <= '1';
01529   end if;
01530  end if;
01531 end process;
01532 
01533 -- commands to the memory
01534 process (clk_0)
01535 begin
01536  if(clk_0'event and clk_0 = '1') then
01537     if(rst = '1') then
01538       ddr_cas_r <= '1';
01539    elsif ((state = LOAD_MODE_REG_ST) or (init_state = INIT_LOAD_MODE_REG_ST) or (read_write_state = '1') or
01540         (init_state = INIT_DUMMY_FIRST_READ) or (init_state = INIT_DUMMY_WRITE) or (state = AUTO_REFRESH) 
01541         or (init_state = INIT_AUTO_REFRESH) or (init_state= INIT_DUMMY_READ) or (init_state = INIT_PATTERN_READ)) then
01542       ddr_cas_r <= '0';
01543    elsif ((state = ACTIVE_WAIT)  or (init_state = INIT_DUMMY_ACTIVE_WAIT)) then
01544       ddr_cas_r <= '1';
01545    else
01546       ddr_cas_r <= '1';
01547   end if;
01548  end if;
01549 end process;
01550 
01551 -- commands to the memory
01552 process (clk_0)
01553 begin
01554  if(clk_0'event and clk_0 = '1') then
01555     if(rst = '1') then
01556       ddr_we_r <= '1';
01557    elsif ((state = LOAD_MODE_REG_ST) or (state = PRECHARGE) or (init_state = INIT_LOAD_MODE_REG_ST) 
01558         or (init_state = INIT_PRECHARGE) or (write_state = '1') or (dummy_write_state = '1')) then
01559       ddr_we_r <= '0';
01560    else ddr_we_r <= '1';
01561   end if;
01562  end if;
01563 end process;
01564 
01565 --register commands to the memory
01566 process (clk_0)
01567 begin
01568  if(clk_0'event and clk_0 = '1') then
01569     if(rst = '1') then
01570       ddr_ras_r2 <= '1';
01571       ddr_cas_r2 <= '1';
01572       ddr_we_r2 <= '1';
01573    else
01574       ddr_ras_r2  <= ddr_ras_r; 
01575       ddr_cas_r2  <= ddr_cas_r;
01576       ddr_we_r2   <= ddr_we_r;
01577   end if;
01578  end if;
01579 end process;
01580            
01581 --register commands to the memory
01582 process (clk_0)
01583 begin
01584  if(clk_0'event and clk_0 = '1') then
01585     if (rst = '1') then 
01586         ddr_ras_r3 <= '1';
01587         ddr_cas_r3 <= '1';
01588         ddr_we_r3  <= '1';
01589    else
01590         ddr_ras_r3  <= ddr_ras_r2; 
01591         ddr_cas_r3  <= ddr_cas_r2;
01592         ddr_we_r3   <= ddr_we_r2;
01593   end if;
01594  end if;
01595 end process;
01596                     
01597 
01598 
01599 process (clk_0)
01600 begin
01601  if(clk_0'event and clk_0 = '1') then
01602    if(rst = '1') then
01603        row_addr_r(row_address-1 downto 0) <= (others => '0');
01604   else
01605        row_addr_r(row_address-1 downto 0) <= af_addr((row_address + col_ap_width)-1 downto col_ap_width);
01606   end if;
01607  end if;
01608 end process;
01609 
01610    
01611 -- address during init 
01612 process (clk_0)
01613 begin
01614  if(clk_0'event and clk_0 = '1') then
01615     if(rst = '1') then
01616        ddr_address_init_r <= (others => '0');
01617    elsif (init_memory = '1') then
01618       if (init_state_r2 = INIT_PRECHARGE) then
01619          ddr_address_init_r <= add_const1((row_address-1) downto 0);--X"0400";         --A10 = 1 for precharge all             
01620       elsif (( init_state_r2 = INIT_LOAD_MODE_REG_ST) and (init_count_cp = "0011")) then
01621          ddr_address_init_r <= ext_mode_reg;                                         -- A0 = 0 for DLL enable  
01622       elsif (( init_state_r2 = INIT_LOAD_MODE_REG_ST) and (init_count_cp = "0100")) then
01623          ddr_address_init_r <= add_const2((row_address-1) downto 0) or load_mode_reg;   -- A8 = 1 for DLL reset
01624       elsif (( init_state_r2 = INIT_LOAD_MODE_REG_ST) and (init_count_cp = "1001")) then
01625          ddr_address_init_r <= add_const5((row_address-1) downto 0) and load_mode_reg;  -- A8 = 0 to deactivate DLL reset
01626       else
01627         ddr_address_init_r <= add_const3((row_address-1) downto 0);
01628       end if;
01629   end if;
01630  end if;
01631 end process;
01632 
01633 
01634 
01635 process (clk_0)
01636 begin
01637  if(clk_0'event and clk_0 = '1') then
01638     if(rst = '1') then
01639       ddr_address_r1 <= (others => '0');
01640    elsif ((state_r2 = ACTIVE)) then
01641       ddr_address_r1 <= row_addr_r;        
01642    elsif (read_write_state_r2 = '1') then
01643       ddr_address_r1 <= af_addr_r(row_address-1 downto 0) and add_const4((row_address-1) downto 0); -- Auto Precharge option is disabled
01644    elsif ((state_r2 = PRECHARGE) or (init_state_r2 = INIT_PRECHARGE)) then
01645       if(PRE_r = '1') then
01646         ddr_address_r1 <= af_addr_r(row_address-1 downto 0);
01647       else 
01648         ddr_address_r1 <= add_const1((row_address-1) downto 0);--X"0400";
01649       end if;
01650    elsif ((state_r2 = LOAD_MODE_REG_ST) or (init_state_r2 = INIT_LOAD_MODE_REG_ST))then
01651       ddr_address_r1 <= af_addr_r(row_address-1 downto 0);
01652    else 
01653       ddr_address_r1 <= add_const3((row_address-1) downto 0);--X"0000";
01654   end if;
01655  end if;
01656 end process;
01657 
01658 process(clk_0)
01659 begin
01660   if(clk_0'event and clk_0 = '1') then
01661      if(rst = '1') then
01662         ddr_address_r2 <= (others =>'0');
01663      elsif(init_memory = '1') then
01664         ddr_address_r2 <= ddr_address_init_r;
01665      else
01666         ddr_address_r2 <= ddr_address_r1;
01667      end if;
01668    end if;
01669 end process;
01670         
01671 process (clk_0)
01672 begin
01673  if(clk_0'event and clk_0 = '1') then
01674     if(rst = '1') then
01675       ddr_ba_r1(bank_address-1 downto 0) <= (others => '0');
01676    elsif (init_memory = '1' and (state_r2 = LOAD_MODE_REG_ST or init_state_r2 = INIT_LOAD_MODE_REG_ST) ) then
01677       if (init_count_cp = "0011") then
01678          ddr_ba_r1(bank_address-1 downto 0) <= "01";--X"1"; 
01679       else 
01680          ddr_ba_r1(bank_address-1 downto 0) <= "00";--X"0";
01681       end if;
01682    elsif ((state_r2 = ACTIVE) or (init_state_r2 = INIT_DUMMY_ACTIVE) or (state_r2 = LOAD_MODE_REG_ST) or 
01683         (init_state_r2 = INIT_LOAD_MODE_REG_ST) or (((state_r2 = PRECHARGE) or (init_state_r2 = INIT_PRECHARGE)) and PRE_r = '1')) then
01684       ddr_ba_r1(bank_address-1 downto 0) <= af_addr((bank_address+row_address + col_ap_width)-1 downto (col_ap_width + row_address)); 
01685    else ddr_ba_r1(bank_address-1 downto 0) <= ddr_ba_r1(bank_address-1 downto 0);
01686   end if;
01687  end if;
01688 end process;
01689 
01690 process(clk_0)
01691 begin
01692   if(clk_0'event and clk_0 = '1') then
01693     if(rst = '1') then
01694         ddr_ba_r2 <= (others => '0');
01695     else
01696         ddr_ba_r2 <= ddr_ba_r1;
01697     end if;
01698   end if;
01699 end process;
01700 
01701 
01702 process (clk_0)
01703 begin
01704  if(clk_0'event and clk_0 = '1') then
01705     if(rst = '1') then
01706       conflict_resolved_r <= '0';
01707    else
01708       if (((state = PRECHARGE_WAIT) or (init_state = INIT_PRECHARGE_WAIT)) and (conflict_detect_r= '1')) then
01709         conflict_resolved_r  <= '1';
01710       elsif(af_rden = '1') then
01711         conflict_resolved_r  <= '0';
01712       end if;
01713   end if;
01714  end if;
01715 end process;
01716 
01717 
01718  process (clk_0)
01719 begin
01720  if(clk_0'event and clk_0 = '1') then
01721     if(rst = '1') then
01722        ddr_cke_r<= '0';
01723    else
01724       if(done_200us = '1') then
01725         ddr_cke_r<= '1';
01726       end if;
01727    end if;
01728  end if;
01729 end process;
01730 
01731 
01732  ctrl_ddr_address(row_address-1 downto 0)  <= ddr_address_r2(row_address-1 downto 0);
01733  ctrl_ddr_ba (bank_address-1 downto 0)     <= ddr_ba_r2(bank_address-1 downto 0);     
01734  ctrl_ddr_ras_L <= ddr_ras_r3;  
01735  ctrl_ddr_cas_L <= ddr_cas_r3;  
01736  ctrl_ddr_we_L  <= ddr_we_r3;   
01737  ctrl_ddr_cs_L <= '0';
01738                                  
01739  ctrl_ddr_cke  <= ddr_cke_r;
01740   
01741 end arch;