00001 --**************************************************************
00002 --* *
00003 --* The source code for the ATLAS BCM "AAA" FPGA is made *
00004 --* available via the GNU General Public License (GPL) *
00005 --* unless otherwise stated below. *
00006 --* *
00007 --* In case of problems/questions/bug reports etc. please *
00008 --* contact michael.niegl@cern.ch *
00009 --* *
00010 --**************************************************************
00011
00012 --**************************************************************
00013 --* *
00014 --* $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/lcd/univibrator.vhd,v $
00015 --* $Revision: 1.4.2.3 $ *
00016 --* $Name: dev $ *
00017 --* $Author: mniegl $ *
00018 --* $Date: 2008/11/03 17:57:46 $ *
00019
00020
00021 --* *
00022 --**************************************************************
00023
00024 library ieee;
00025
00026 use ieee.std_logic_1164.all;
00027
00028 use ieee.std_logic_arith.all;
00029
00030 use ieee.std_logic_unsigned.all;
00031
00032
00033 entity univibrator is
00034 port (CLOCK : in ;
00035 TRIGER : in ;
00036 SIGNAL_OUT : out := '0'
00037 );
00038 end univibrator;
00039
00040
00041 architecture univibrator_arc of univibrator is
00042
00043 signal int_operate : := '0';
00044 signal int_latch : := '0';
00045 signal int_count : (2 downto 0) := "000";
00046
00047 begin
00048
00049
00050 rising_clock : process (CLOCK) is --positive edges
00051 begin
00052 if (CLOCK'event and CLOCK = '1') then --rising edge
00053 if int_latch = '0' and TRIGER = '1' then --rising edge of TRIGGER detected
00054 int_operate <= '1';
00055 SIGNAL_OUT <= '1';
00056 int_count <= "000";
00057 end if;
00058 if int_operate = '1' then
00059 int_count <= int_count + 1;
00060 if int_count = "011" then --end of signal
00061 int_operate <= '0';
00062 SIGNAL_OUT <= '0';
00063 end if;
00064 end if;
00065 int_latch <= TRIGER;
00066 end if;
00067 end process;
00068
00069 end univibrator_arc;
00070