BCM-AAA: rocketio_sata.vhd Source File

00001 --**************************************************************
00002 --*                                                            *
00003 --*     The source code for the ATLAS BCM "AAA" FPGA is made   *
00004 --*     available via the GNU General Public License (GPL)     *
00005 --*     unless otherwise stated below.                         *
00006 --*                                                            *
00007 --*     In case of problems/questions/bug reports etc. please  *
00008 --*     contact michael.niegl@cern.ch                          *
00009 --*                                                            *
00010 --**************************************************************
00011 
00012 --**************************************************************
00013 --*                                                            *
00014 --*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/sata/rocketio_sata.vhd,v $
00015 --*  $Revision: 1.8.2.6 $                                      *
00016 --*  $Name: dev $                                              *
00017 --*  $Author: mniegl $                                         *
00018 --*  $Date: 2008/11/03 17:57:49 $                              *
00019 
00020 
00021 --*                                                            *
00022 --**************************************************************
00023 -------------------------------------------------------------------------------
00024 --$Date: 2008/11/03 17:57:49 $
00025 --$RCSfile: rocketio_sata.vhd,v $
00026 --$Revision: 1.8.2.6 $
00027 --------------------------------------------------------------------------------
00028 --   __  __ 
00029 --  /   /\/   / 
00030 -- /__/  \  /    Vendor: Xilinx 
00031 -- \   \   \/     Version : 1.4
00032 --  \   \         Application : RocketIO Wizard 
00033 --  /   /         Filename : rocketio_sata.vhd
00034 -- /__/   /\     Timestamp : 02/08/2005 09:12:43
00035 -- \   \  /  \ 
00036 --  \__\/\__\ 
00037 --
00038 --
00039 -- Module ROCKETIO_SATA (an MGT Wrapper)
00040 -- Generated by Xilinx RocketIO Wizard
00041 
00042 
00043 library ieee;
00044 
00045 use ieee.std_logic_1164.all;
00046 
00047 use ieee.numeric_std.all;
00048 -- synopsys translate_off
00049 
00050 library unisim;
00051 
00052 use unisim.vcomponents.all;
00053 -- synopsys translate_on
00054 
00055 
00056 entity ROCKETIO_SATA is
00057   generic
00058     (
00059       SIMULATION_P     : integer                       := 0;
00060       TX_FD_MIN_P      : std_logic_vector(10 downto 0) := "00001001101";
00061       TX_FD_EN_P       : std_logic                     := '1';
00062       RX_FD_MIN_P      : std_logic_vector(10 downto 0) := "00001001101";
00063       RX_FD_EN_P       : std_logic                     := '1';
00064       TX_FD_WIDTH_P    : integer                       := 11;
00065       RX_FD_WIDTH_P    : integer                       := 11;
00066       MGT0_GT11_MODE_P : string                        := "B";
00067       MGT0_MGT_ID_P    : integer                       := 1;
00068       MGT1_GT11_MODE_P : string                        := "A";
00069       MGT1_MGT_ID_P    : integer                       := 0
00070       );
00071   port
00072     (
00073       RXCOMMADETUSE0_IN        : in  std_logic;
00074       RXCOMMADETUSE1_IN        : in  std_logic;
00075       --------------------------------- CRC Ports --------------------------------
00076       MGT_TXCRCCLK_IN          : in  std_logic;
00077       MGT0_TXCRCDATAVALID_IN   : in  std_logic;
00078       MGT1_TXCRCDATAVALID_IN   : in  std_logic;
00079       MGT0_TXCRCINIT_IN        : in  std_logic;
00080       MGT1_TXCRCINIT_IN        : in  std_logic;
00081       MGT_TXCRCINTCLK_IN       : in  std_logic;
00082       MGT0_TXCRCOUT_OUT        : out std_logic_vector(31 downto 0);
00083       MGT1_TXCRCOUT_OUT        : out std_logic_vector(31 downto 0);
00084       MGT0_TXCRCRESET_IN       : in  std_logic;
00085       MGT1_TXCRCRESET_IN       : in  std_logic;
00086       MGT_RXCRCCLK_IN          : in  std_logic;
00087       MGT0_RXCRCDATAVALID_IN   : in  std_logic;
00088       MGT1_RXCRCDATAVALID_IN   : in  std_logic;
00089       MGT0_RXCRCIN_IN          : in  std_logic_vector(31 downto 0);
00090       MGT1_RXCRCIN_IN          : in  std_logic_vector(31 downto 0);
00091       MGT0_RXCRCINIT_IN        : in  std_logic;
00092       MGT1_RXCRCINIT_IN        : in  std_logic;
00093       MGT_RXCRCINTCLK_IN       : in  std_logic;
00094       MGT0_RXCRCOUT_OUT        : out std_logic_vector(31 downto 0);
00095       MGT1_RXCRCOUT_OUT        : out std_logic_vector(31 downto 0);
00096       MGT0_RXCRCRESET_IN       : in  std_logic;
00097       MGT1_RXCRCRESET_IN       : in  std_logic;
00098       --__________________________________________________________________________
00099       --__________________________________________________________________________
00100       --MGT0  (X0Y0)
00101       ----------------- 8B10B Receive Data Path and Control Ports ----------------
00102       MGT0_RXCHARISCOMMA_OUT   : out std_logic_vector(3 downto 0);
00103       MGT0_RXCHARISK_OUT       : out std_logic_vector(3 downto 0);
00104       MGT0_RXDATA_OUT          : out std_logic_vector(31 downto 0);
00105       MGT0_RXDISPERR_OUT       : out std_logic_vector(3 downto 0);
00106       MGT0_RXNOTINTABLE_OUT    : out std_logic_vector(3 downto 0);
00107       MGT0_RXRUNDISP_OUT       : out std_logic_vector(3 downto 0);
00108       ----------------- 8B10B Transmit Data Path and Control Ports ---------------
00109       MGT0_TXBYPASS8B10B_IN    : in  std_logic_vector(3 downto 0);
00110       MGT0_TXCHARDISPMODE_IN   : in  std_logic_vector(3 downto 0);
00111       MGT0_TXCHARDISPVAL_IN    : in  std_logic_vector(3 downto 0);
00112       MGT0_TXCHARISK_IN        : in  std_logic_vector(3 downto 0);
00113       MGT0_TXDATA_IN           : in  std_logic_vector(31 downto 0);
00114       MGT0_TXKERR_OUT          : out std_logic_vector(3 downto 0);
00115       MGT0_TXRUNDISP_OUT       : out std_logic_vector(3 downto 0);
00116       -------------------------- Calibration Block Ports -------------------------
00117       MGT0_ACTIVE_OUT          : out std_logic;
00118       MGT0_DISABLE_IN          : in  std_logic;
00119       MGT0_DRP_RESET_IN        : in  std_logic;
00120       MGT0_RX_SIGNAL_DETECT_IN : in  std_logic;
00121       MGT0_TX_SIGNAL_DETECT_IN : in  std_logic;
00122       ----------------------------- Calibration Ports ----------------------------
00123       MGT0_RXCLKSTABLE_IN      : in  std_logic;
00124       MGT0_TXCLKSTABLE_IN      : in  std_logic;
00125       --------------------- Dynamic Reconfiguration Port (DRP) -------------------
00126       MGT0_DADDR_IN            : in  std_logic_vector(7 downto 0);
00127       MGT0_DCLK_IN             : in  std_logic;
00128       MGT0_DEN_IN              : in  std_logic;
00129       MGT0_DI_IN               : in  std_logic_vector(15 downto 0);
00130       MGT0_DO_OUT              : out std_logic_vector(15 downto 0);
00131       MGT0_DRDY_OUT            : out std_logic;
00132       MGT0_DWE_IN              : in  std_logic;
00133       -------------------------------- Global Ports ------------------------------
00134       MGT0_LOOPBACK_IN         : in  std_logic_vector(1 downto 0);
00135       MGT0_POWERDOWN_IN        : in  std_logic;
00136       MGT0_TXINHIBIT_IN        : in  std_logic;
00137       ------------------------ Out of Band Signalling Ports ----------------------
00138       MGT0_RXSIGDET_OUT        : out std_logic;
00139       MGT0_TXENOOB_IN          : in  std_logic;
00140       ---------------------------------- PLL Lock --------------------------------
00141       MGT0_RXLOCK_OUT          : out std_logic;
00142       MGT0_TXLOCK_OUT          : out std_logic;
00143       --------------------------- Polarity Control Ports -------------------------
00144       MGT0_RXPOLARITY_IN       : in  std_logic;
00145       MGT0_TXPOLARITY_IN       : in  std_logic;
00146       ---------------------------- Ports for Simulation --------------------------
00147       MGT0_COMBUSIN_IN         : in  std_logic_vector(15 downto 0);
00148       MGT0_COMBUSOUT_OUT       : out std_logic_vector(15 downto 0);
00149       ------------------------------ Reference Clocks ----------------------------
00150       MGT0_REFCLK1_IN          : in  std_logic;
00151       ----------------------------------- Resets ---------------------------------
00152       MGT0_RXPMARESET_IN       : in  std_logic;
00153       MGT0_RXRESET_IN          : in  std_logic;
00154       MGT0_TXPMARESET_IN       : in  std_logic;
00155       MGT0_TXRESET_IN          : in  std_logic;
00156       ------------------------------ Serdes Alignment ----------------------------
00157       MGT0_ENMCOMMAALIGN_IN    : in  std_logic;
00158       MGT0_ENPCOMMAALIGN_IN    : in  std_logic;
00159       MGT0_RXCOMMADET_OUT      : out std_logic;
00160       MGT0_RXREALIGN_OUT       : out std_logic;
00161       -------------------------------- Serial Ports ------------------------------
00162       MGT0_RX1N_IN             : in  std_logic;
00163       MGT0_RX1P_IN             : in  std_logic;
00164       MGT0_TX1N_OUT            : out std_logic;
00165       MGT0_TX1P_OUT            : out std_logic;
00166       ----------------------------------- Status ---------------------------------
00167       MGT0_RXSTATUS_OUT        : out std_logic_vector(5 downto 0);
00168       ------------------------------ Synchronization -----------------------------
00169       MGT0_RXSYNC_IN           : in  std_logic;
00170       MGT0_TXSYNC_IN           : in  std_logic;
00171       -------------------------------- User Clocks -------------------------------
00172       MGT0_RXRECCLK1_OUT       : out std_logic;
00173       MGT0_RXRECCLK2_OUT       : out std_logic;
00174       MGT0_RXUSRCLK2_IN        : in  std_logic;
00175       MGT0_TXOUTCLK1_OUT       : out std_logic;
00176       MGT0_TXOUTCLK2_OUT       : out std_logic;
00177       MGT0_TXUSRCLK2_IN        : in  std_logic;
00178       --__________________________________________________________________________
00179       --__________________________________________________________________________
00180       --MGT1  (X0Y1)
00181       ----------------- 8B10B Receive Data Path and Control Ports ----------------
00182       MGT1_RXCHARISCOMMA_OUT   : out std_logic_vector(3 downto 0);
00183       MGT1_RXCHARISK_OUT       : out std_logic_vector(3 downto 0);
00184       MGT1_RXDATA_OUT          : out std_logic_vector(31 downto 0);
00185       MGT1_RXDISPERR_OUT       : out std_logic_vector(3 downto 0);
00186       MGT1_RXNOTINTABLE_OUT    : out std_logic_vector(3 downto 0);
00187       MGT1_RXRUNDISP_OUT       : out std_logic_vector(3 downto 0);
00188       ----------------- 8B10B Transmit Data Path and Control Ports ---------------
00189       MGT1_TXBYPASS8B10B_IN    : in  std_logic_vector(3 downto 0);
00190       MGT1_TXCHARDISPMODE_IN   : in  std_logic_vector(3 downto 0);
00191       MGT1_TXCHARDISPVAL_IN    : in  std_logic_vector(3 downto 0);
00192       MGT1_TXCHARISK_IN        : in  std_logic_vector(3 downto 0);
00193       MGT1_TXDATA_IN           : in  std_logic_vector(31 downto 0);
00194       MGT1_TXKERR_OUT          : out std_logic_vector(3 downto 0);
00195       MGT1_TXRUNDISP_OUT       : out std_logic_vector(3 downto 0);
00196       -------------------------- Calibration Block Ports -------------------------
00197       MGT1_ACTIVE_OUT          : out std_logic;
00198       MGT1_DISABLE_IN          : in  std_logic;
00199       MGT1_DRP_RESET_IN        : in  std_logic;
00200       MGT1_RX_SIGNAL_DETECT_IN : in  std_logic;
00201       MGT1_TX_SIGNAL_DETECT_IN : in  std_logic;
00202       ----------------------------- Calibration Ports ----------------------------
00203       MGT1_RXCLKSTABLE_IN      : in  std_logic;
00204       MGT1_TXCLKSTABLE_IN      : in  std_logic;
00205       --------------------- Dynamic Reconfiguration Port (DRP) -------------------
00206       MGT1_DADDR_IN            : in  std_logic_vector(7 downto 0);
00207       MGT1_DCLK_IN             : in  std_logic;
00208       MGT1_DEN_IN              : in  std_logic;
00209       MGT1_DI_IN               : in  std_logic_vector(15 downto 0);
00210       MGT1_DO_OUT              : out std_logic_vector(15 downto 0);
00211       MGT1_DRDY_OUT            : out std_logic;
00212       MGT1_DWE_IN              : in  std_logic;
00213       -------------------------------- Global Ports ------------------------------
00214       MGT1_LOOPBACK_IN         : in  std_logic_vector(1 downto 0);
00215       MGT1_POWERDOWN_IN        : in  std_logic;
00216       MGT1_TXINHIBIT_IN        : in  std_logic;
00217       ------------------------ Out of Band Signalling Ports ----------------------
00218       MGT1_RXSIGDET_OUT        : out std_logic;
00219       MGT1_TXENOOB_IN          : in  std_logic;
00220       ---------------------------------- PLL Lock --------------------------------
00221       MGT1_RXLOCK_OUT          : out std_logic;
00222       MGT1_TXLOCK_OUT          : out std_logic;
00223       --------------------------- Polarity Control Ports -------------------------
00224       MGT1_RXPOLARITY_IN       : in  std_logic;
00225       MGT1_TXPOLARITY_IN       : in  std_logic;
00226       ---------------------------- Ports for Simulation --------------------------
00227       MGT1_COMBUSIN_IN         : in  std_logic_vector(15 downto 0);
00228       MGT1_COMBUSOUT_OUT       : out std_logic_vector(15 downto 0);
00229       ------------------------------ Reference Clocks ----------------------------
00230       MGT1_REFCLK1_IN          : in  std_logic;
00231       ----------------------------------- Resets ---------------------------------
00232       MGT1_RXPMARESET_IN       : in  std_logic;
00233       MGT1_RXRESET_IN          : in  std_logic;
00234       MGT1_TXPMARESET_IN       : in  std_logic;
00235       MGT1_TXRESET_IN          : in  std_logic;
00236       ------------------------------ Serdes Alignment ----------------------------
00237       MGT1_ENMCOMMAALIGN_IN    : in  std_logic;
00238       MGT1_ENPCOMMAALIGN_IN    : in  std_logic;
00239       MGT1_RXCOMMADET_OUT      : out std_logic;
00240       MGT1_RXREALIGN_OUT       : out std_logic;
00241       -------------------------------- Serial Ports ------------------------------
00242       MGT1_RX1N_IN             : in  std_logic;
00243       MGT1_RX1P_IN             : in  std_logic;
00244       MGT1_TX1N_OUT            : out std_logic;
00245       MGT1_TX1P_OUT            : out std_logic;
00246       ----------------------------------- Status ---------------------------------
00247       MGT1_RXSTATUS_OUT        : out std_logic_vector(5 downto 0);
00248       ------------------------------ Synchronization -----------------------------
00249       MGT1_RXSYNC_IN           : in  std_logic;
00250       MGT1_TXSYNC_IN           : in  std_logic;
00251       -------------------------------- User Clocks -------------------------------
00252       MGT1_RXRECCLK1_OUT       : out std_logic;
00253       MGT1_RXRECCLK2_OUT       : out std_logic;
00254       MGT1_RXUSRCLK2_IN        : in  std_logic;
00255       MGT1_TXOUTCLK1_OUT       : out std_logic;
00256       MGT1_TXOUTCLK2_OUT       : out std_logic;
00257       MGT1_TXUSRCLK2_IN        : in  std_logic
00258       );
00259 end ROCKETIO_SATA;
00260 
00261 
00262 architecture ROCKETIO_SATA_arc of ROCKETIO_SATA is
00263 --************************** Parameter Declarations ****************************
00264 
00265   constant RXDATAWIDTH_P    : std_logic_vector := "10";
00266   constant TXDATAWIDTH_P    : std_logic_vector := "10";
00267   constant RXINTDATAWIDTH_P : std_logic_vector := "11";
00268   constant TXINTDATAWIDTH_P : std_logic_vector := "11";
00269 
00270 --***************************** Signal Declarations *****************************
00271 
00272   -- ground and tied_to_vcc_i signals
00273   signal tied_to_ground_i               : std_logic;
00274   signal tied_to_ground_vec_i           : std_logic_vector(31 downto 0);
00275   signal tied_to_vcc_i                  : std_logic;
00276   -- channel bond signals
00277   signal mgt0_chbondo_i                 : std_logic_vector(4 downto 0);
00278   -- drp connection signals
00279   signal mgt0_daddr_i                   : std_logic_vector(7 downto 0);
00280   signal mgt0_den_i                     : std_logic;
00281   signal mgt0_di_i                      : std_logic_vector(15 downto 0);
00282   signal mgt0_do_i                      : std_logic_vector(15 downto 0);
00283   signal mgt0_drdy_i                    : std_logic;
00284   signal mgt0_dwe_i                     : std_logic;
00285   signal mgt0_rxlock_i                  : std_logic;
00286   signal mgt0_txlock_i                  : std_logic;
00287   signal mgt0_loopback_i                : std_logic_vector(1 downto 0);
00288   signal mgt0_txenc8b10buse_i           : std_logic;
00289   signal mgt0_txbypass8b10b_i           : std_logic_vector(7 downto 0);
00290   signal mgt0_rxpmareset_i              : std_logic;
00291   signal mgt0_txpmareset_i              : std_logic;
00292   signal mgt0_txoutclk1_i               : std_logic;
00293   signal mgt0_rxrecclk2_i               : std_logic;
00294   signal mgt0_rxchariscomma_out_float_i : std_logic_vector(3 downto 0);
00295   signal mgt0_rxcharisk_out_float_i     : std_logic_vector(3 downto 0);
00296   signal mgt0_rxdata_out_float_i        : std_logic_vector(31 downto 0);
00297   signal mgt0_rxdisperr_out_float_i     : std_logic_vector(3 downto 0);
00298   signal mgt0_rxnotintable_out_float_i  : std_logic_vector(3 downto 0);
00299   signal mgt0_rxrundisp_out_float_i     : std_logic_vector(3 downto 0);
00300   signal mgt0_txkerr_out_float_i        : std_logic_vector(3 downto 0);
00301   signal mgt0_txrundisp_out_float_i     : std_logic_vector(3 downto 0);
00302   -- channel bond signals
00303   signal mgt1_chbondo_i                 : std_logic_vector(4 downto 0);
00304   -- drp connection signals
00305   signal mgt1_daddr_i                   : std_logic_vector(7 downto 0);
00306   signal mgt1_den_i                     : std_logic;
00307   signal mgt1_di_i                      : std_logic_vector(15 downto 0);
00308   signal mgt1_do_i                      : std_logic_vector(15 downto 0);
00309   signal mgt1_drdy_i                    : std_logic;
00310   signal mgt1_dwe_i                     : std_logic;
00311   signal mgt1_rxlock_i                  : std_logic;
00312   signal mgt1_txlock_i                  : std_logic;
00313   signal mgt1_loopback_i                : std_logic_vector(1 downto 0);
00314   signal mgt1_txenc8b10buse_i           : std_logic;
00315   signal mgt1_txbypass8b10b_i           : std_logic_vector(7 downto 0);
00316   signal mgt1_rxpmareset_i              : std_logic;
00317   signal mgt1_txpmareset_i              : std_logic;
00318   signal mgt1_txoutclk1_i               : std_logic;
00319   signal mgt1_rxrecclk2_i               : std_logic;
00320   signal mgt1_rxchariscomma_out_float_i : std_logic_vector(3 downto 0);
00321   signal mgt1_rxcharisk_out_float_i     : std_logic_vector(3 downto 0);
00322   signal mgt1_rxdata_out_float_i        : std_logic_vector(31 downto 0);
00323   signal mgt1_rxdisperr_out_float_i     : std_logic_vector(3 downto 0);
00324   signal mgt1_rxnotintable_out_float_i  : std_logic_vector(3 downto 0);
00325   signal mgt1_rxrundisp_out_float_i     : std_logic_vector(3 downto 0);
00326   signal mgt1_txkerr_out_float_i        : std_logic_vector(3 downto 0);
00327   signal mgt1_txrundisp_out_float_i     : std_logic_vector(3 downto 0);
00328 
00329 --**************************** Component Declarations ***************************
00330 
00331 
00332   component GT11
00333     generic
00334       (
00335         ALIGN_COMMA_WORD        : integer    := 1;
00336         BANDGAPSEL              : boolean    := false;
00337         BIASRESSEL              : boolean    := true;
00338         CCCB_ARBITRATOR_DISABLE : boolean    := false;
00339         CHAN_BOND_LIMIT         : integer    := 16;
00340         CHAN_BOND_MODE          : string     := "NONE";
00341         CHAN_BOND_ONE_SHOT      : boolean    := false;
00342         CHAN_BOND_SEQ_1_1       : bit_vector := "00000000000";
00343         CHAN_BOND_SEQ_1_2       : bit_vector := "00000000000";
00344         CHAN_BOND_SEQ_1_3       : bit_vector := "00000000000";
00345         CHAN_BOND_SEQ_1_4       : bit_vector := "00000000000";
00346         CHAN_BOND_SEQ_1_MASK    : bit_vector := "0000";
00347         CHAN_BOND_SEQ_2_1       : bit_vector := "00000000000";
00348         CHAN_BOND_SEQ_2_2       : bit_vector := "00000000000";
00349         CHAN_BOND_SEQ_2_3       : bit_vector := "00000000000";
00350         CHAN_BOND_SEQ_2_4       : bit_vector := "00000000000";
00351         CHAN_BOND_SEQ_2_MASK    : bit_vector := "0000";
00352         CHAN_BOND_SEQ_2_USE     : boolean    := false;
00353         CHAN_BOND_SEQ_LEN       : integer    := 1;
00354         CLK_COR_8B10B_DE        : boolean    := false;
00355         CLK_COR_MAX_LAT         : integer    := 48;
00356         CLK_COR_MIN_LAT         : integer    := 36;
00357         CLK_COR_SEQ_1_1         : bit_vector := "00000000000";
00358         CLK_COR_SEQ_1_2         : bit_vector := "00000000000";
00359         CLK_COR_SEQ_1_3         : bit_vector := "00000000000";
00360         CLK_COR_SEQ_1_4         : bit_vector := "00000000000";
00361         CLK_COR_SEQ_1_MASK      : bit_vector := "0000";
00362         CLK_COR_SEQ_2_1         : bit_vector := "00000000000";
00363         CLK_COR_SEQ_2_2         : bit_vector := "00000000000";
00364         CLK_COR_SEQ_2_3         : bit_vector := "00000000000";
00365         CLK_COR_SEQ_2_4         : bit_vector := "00000000000";
00366         CLK_COR_SEQ_2_MASK      : bit_vector := "0000";
00367         CLK_COR_SEQ_2_USE       : boolean    := false;
00368         CLK_COR_SEQ_DROP        : boolean    := false;
00369         CLK_COR_SEQ_LEN         : integer    := 1;
00370         CLK_CORRECT_USE         : boolean    := true;
00371         COMMA_10B_MASK          : bit_vector := x"3FF";
00372         COMMA32                 : boolean    := false;
00373         CYCLE_LIMIT_SEL         : bit_vector := "00";
00374         DCDR_FILTER             : bit_vector := "010";
00375         DEC_MCOMMA_DETECT       : boolean    := true;
00376         DEC_PCOMMA_DETECT       : boolean    := true;
00377         DEC_VALID_COMMA_ONLY    : boolean    := true;
00378         DIGRX_FWDCLK            : bit_vector := "00";
00379         DIGRX_SYNC_MODE         : boolean    := false;
00380         ENABLE_DCDR             : boolean    := false;
00381         FDET_HYS_CAL            : bit_vector := "110";
00382         FDET_HYS_SEL            : bit_vector := "110";
00383         FDET_LCK_CAL            : bit_vector := "101";
00384         FDET_LCK_SEL            : bit_vector := "101";
00385         GT11_MODE               : string     := "DONT_CARE";
00386         IREFBIASMODE            : bit_vector := "11";
00387         LOOPCAL_WAIT            : bit_vector := "00";
00388         MCOMMA_32B_VALUE        : bit_vector := x"000000F6";
00389         MCOMMA_DETECT           : boolean    := true;
00390         OPPOSITE_SELECT         : boolean    := false;
00391         PCOMMA_32B_VALUE        : bit_vector := x"F6F62828";
00392         PCOMMA_DETECT           : boolean    := true;
00393         PCS_BIT_SLIP            : boolean    := false;
00394         PMA_BIT_SLIP            : boolean    := false;
00395         PMACLKENABLE            : boolean    := true;
00396         PMACOREPWRENABLE        : boolean    := true;
00397         PMAIREFTRIM             : bit_vector := "0111";
00398         PMAVBGCTRL              : bit_vector := "00000";
00399         PMAVREFTRIM             : bit_vector := "0111";
00400         POWER_ENABLE            : boolean    := true;
00401         REPEATER                : boolean    := false;
00402         RX_BUFFER_USE           : boolean    := true;
00403         RX_CLOCK_DIVIDER        : bit_vector := "00";
00404         RXACTST                 : boolean    := false;
00405         RXAFEEQ                 : bit_vector := "000000000";
00406         RXAFEPD                 : boolean    := false;
00407         RXAFETST                : boolean    := false;
00408         RXAPD                   : boolean    := false;
00409         RXASYNCDIVIDE           : bit_vector := "11";
00410         RXBY_32                 : boolean    := true;
00411         RXCDRLOS                : bit_vector := "000000";
00412         RXCLK0_FORCE_PMACLK     : boolean    := false;
00413         RXCLKMODE               : bit_vector := "000010";
00414         RXCMADJ                 : bit_vector := "10";
00415         RXCPSEL                 : boolean    := true;
00416         RXCPTST                 : boolean    := false;
00417         RXCRCCLOCKDOUBLE        : boolean    := false;
00418         RXCRCENABLE             : boolean    := false;
00419         RXCRCINITVAL            : bit_vector := x"00000000";
00420         RXCRCINVERTGEN          : boolean    := false;
00421         RXCRCSAMECLOCK          : boolean    := false;
00422         RXCTRL1                 : bit_vector := x"200";
00423         RXCYCLE_LIMIT_SEL       : bit_vector := "00";
00424         RXDATA_SEL              : bit_vector := "00";
00425         RXDCCOUPLE              : boolean    := false;
00426         RXDIGRESET              : boolean    := false;
00427         RXDIGRX                 : boolean    := false;
00428         RXEQ                    : bit_vector := x"4000000000000000";
00429         RXFDCAL_CLOCK_DIVIDE    : string     := "NONE";
00430         RXFDET_HYS_CAL          : bit_vector := "110";
00431         RXFDET_HYS_SEL          : bit_vector := "110";
00432         RXFDET_LCK_CAL          : bit_vector := "101";
00433         RXFDET_LCK_SEL          : bit_vector := "101";
00434         RXFECONTROL1            : bit_vector := "00";
00435         RXFECONTROL2            : bit_vector := "000";
00436         RXFETUNE                : bit_vector := "01";
00437         RXLB                    : boolean    := false;
00438         RXLKADJ                 : bit_vector := "00000";
00439         RXLKAPD                 : boolean    := false;
00440         RXLOOPCAL_WAIT          : bit_vector := "00";
00441         RXLOOPFILT              : bit_vector := "0111";
00442         RXOUTDIV2SEL            : integer    := 1;
00443         RXPD                    : boolean    := false;
00444         RXPDDTST                : boolean    := false;
00445         RXPLLNDIVSEL            : integer    := 8;
00446         RXPMACLKSEL             : string     := "REFCLK1";
00447         RXRCPADJ                : bit_vector := "011";
00448         RXRCPPD                 : boolean    := false;
00449         RXRECCLK1_USE_SYNC      : boolean    := false;
00450         RXRIBADJ                : bit_vector := "11";
00451         RXRPDPD                 : boolean    := false;
00452         RXRSDPD                 : boolean    := false;
00453         RXSLOWDOWN_CAL          : bit_vector := "00";
00454         RXUSRDIVISOR            : integer    := 1;
00455         RXVCO_CTRL_ENABLE       : boolean    := true;
00456         RXVCODAC_INIT           : bit_vector := "1010000000";
00457         SAMPLE_8X               : boolean    := false;
00458         SH_CNT_MAX              : integer    := 64;
00459         SH_INVALID_CNT_MAX      : integer    := 16;
00460         SLOWDOWN_CAL            : bit_vector := "00";
00461         TX_BUFFER_USE           : boolean    := true;
00462         TX_CLOCK_DIVIDER        : bit_vector := "00";
00463         TXABPMACLKSEL           : string     := "REFCLK1";
00464         TXAPD                   : boolean    := false;
00465         TXAREFBIASSEL           : boolean    := false;
00466         TXASYNCDIVIDE           : bit_vector := "11";
00467         TXCLK0_FORCE_PMACLK     : boolean    := false;
00468         TXCLKMODE               : bit_vector := "1001";
00469         TXCPSEL                 : boolean    := true;
00470         TXCRCCLOCKDOUBLE        : boolean    := false;
00471         TXCRCENABLE             : boolean    := false;
00472         TXCRCINITVAL            : bit_vector := x"00000000";
00473         TXCRCINVERTGEN          : boolean    := false;
00474         TXCRCSAMECLOCK          : boolean    := false;
00475         TXCTRL1                 : bit_vector := x"200";
00476         TXDAT_PRDRV_DAC         : bit_vector := "111";
00477         TXDAT_TAP_DAC           : bit_vector := "10110";
00478         TXDATA_SEL              : bit_vector := "00";
00479         TXDIGPD                 : boolean    := false;
00480         TXFDCAL_CLOCK_DIVIDE    : string     := "NONE";
00481         TXHIGHSIGNALEN          : boolean    := true;
00482         TXLOOPFILT              : bit_vector := "0111";
00483         TXLVLSHFTPD             : boolean    := false;
00484         TXOUTCLK1_USE_SYNC      : boolean    := false;
00485         TXOUTDIV2SEL            : integer    := 1;
00486         TXPD                    : boolean    := false;
00487         TXPHASESEL              : boolean    := false;
00488         TXPLLNDIVSEL            : integer    := 8;
00489         TXPOST_PRDRV_DAC        : bit_vector := "111";
00490         TXPOST_TAP_DAC          : bit_vector := "01110";
00491         TXPOST_TAP_PD           : boolean    := true;
00492         TXPRE_PRDRV_DAC         : bit_vector := "111";
00493         TXPRE_TAP_DAC           : bit_vector := "00000";
00494         TXPRE_TAP_PD            : boolean    := true;
00495         TXSLEWRATE              : boolean    := false;
00496         TXTERMTRIM              : bit_vector := "1100";
00497         VCO_CTRL_ENABLE         : boolean    := true;
00498         VCODAC_INIT             : bit_vector := "1010000000";
00499         VREFBIASMODE            : bit_vector := "11"
00500         );
00501     port
00502       (
00503         CHBONDI              : in  std_logic_vector (4 downto 0);
00504         ENCHANSYNC           : in  std_logic;
00505         ENMCOMMAALIGN        : in  std_logic;
00506         ENPCOMMAALIGN        : in  std_logic;
00507         LOOPBACK             : in  std_logic_vector (1 downto 0);
00508         POWERDOWN            : in  std_logic;
00509         RXBLOCKSYNC64B66BUSE : in  std_logic;
00510         RXCOMMADETUSE        : in  std_logic;
00511         RXDATAWIDTH          : in  std_logic_vector (1 downto 0);
00512         RXDEC64B66BUSE       : in  std_logic;
00513         RXDEC8B10BUSE        : in  std_logic;
00514         RXDESCRAM64B66BUSE   : in  std_logic;
00515         RXIGNOREBTF          : in  std_logic;
00516         RXINTDATAWIDTH       : in  std_logic_vector (1 downto 0);
00517         RXPOLARITY           : in  std_logic;
00518         RXRESET              : in  std_logic;
00519         RXSLIDE              : in  std_logic;
00520         RXUSRCLK             : in  std_logic;
00521         RXUSRCLK2            : in  std_logic;
00522         TXBYPASS8B10B        : in  std_logic_vector (7 downto 0);
00523         TXCHARDISPMODE       : in  std_logic_vector (7 downto 0);
00524         TXCHARDISPVAL        : in  std_logic_vector (7 downto 0);
00525         TXCHARISK            : in  std_logic_vector (7 downto 0);
00526         TXDATA               : in  std_logic_vector (63 downto 0);
00527         TXDATAWIDTH          : in  std_logic_vector (1 downto 0);
00528         TXENC64B66BUSE       : in  std_logic;
00529         TXENC8B10BUSE        : in  std_logic;
00530         TXGEARBOX64B66BUSE   : in  std_logic;
00531         TXINHIBIT            : in  std_logic;
00532         TXINTDATAWIDTH       : in  std_logic_vector (1 downto 0);
00533         TXPOLARITY           : in  std_logic;
00534         TXRESET              : in  std_logic;
00535         TXSCRAM64B66BUSE     : in  std_logic;
00536         TXUSRCLK             : in  std_logic;
00537         TXUSRCLK2            : in  std_logic;
00538         RXCLKSTABLE          : in  std_logic;
00539         RXPMARESET           : in  std_logic;
00540         TXCLKSTABLE          : in  std_logic;
00541         TXPMARESET           : in  std_logic;
00542         RXCRCIN              : in  std_logic_vector (63 downto 0);
00543         RXCRCDATAWIDTH       : in  std_logic_vector (2 downto 0);
00544         RXCRCDATAVALID       : in  std_logic;
00545         RXCRCINIT            : in  std_logic;
00546         RXCRCRESET           : in  std_logic;
00547         RXCRCPD              : in  std_logic;
00548         RXCRCCLK             : in  std_logic;
00549         RXCRCINTCLK          : in  std_logic;
00550         TXCRCIN              : in  std_logic_vector (63 downto 0);
00551         TXCRCDATAWIDTH       : in  std_logic_vector (2 downto 0);
00552         TXCRCDATAVALID       : in  std_logic;
00553         TXCRCINIT            : in  std_logic;
00554         TXCRCRESET           : in  std_logic;
00555         TXCRCPD              : in  std_logic;
00556         TXCRCCLK             : in  std_logic;
00557         TXCRCINTCLK          : in  std_logic;
00558         TXSYNC               : in  std_logic;
00559         RXSYNC               : in  std_logic;
00560         TXENOOB              : in  std_logic;
00561         DCLK                 : in  std_logic;
00562         DADDR                : in  std_logic_vector (7 downto 0);
00563         DEN                  : in  std_logic;
00564         DWE                  : in  std_logic;
00565         DI                   : in  std_logic_vector (15 downto 0);
00566         RX1P                 : in  std_logic;
00567         RX1N                 : in  std_logic;
00568         GREFCLK              : in  std_logic;
00569         REFCLK1              : in  std_logic;
00570         REFCLK2              : in  std_logic;
00571         CHBONDO              : out std_logic_vector (4 downto 0);
00572         RXSTATUS             : out std_logic_vector (5 downto 0);
00573         RXCHARISCOMMA        : out std_logic_vector (7 downto 0);
00574         RXCHARISK            : out std_logic_vector (7 downto 0);
00575         RXCOMMADET           : out std_logic;
00576         RXDATA               : out std_logic_vector (63 downto 0);
00577         RXDISPERR            : out std_logic_vector (7 downto 0);
00578         RXLOSSOFSYNC         : out std_logic_vector (1 downto 0);
00579         RXNOTINTABLE         : out std_logic_vector (7 downto 0);
00580         RXREALIGN            : out std_logic;
00581         RXRUNDISP            : out std_logic_vector (7 downto 0);
00582         RXBUFERR             : out std_logic;
00583         TXBUFERR             : out std_logic;
00584         TXKERR               : out std_logic_vector (7 downto 0);
00585         TXRUNDISP            : out std_logic_vector (7 downto 0);
00586         RXRECCLK1            : out std_logic;
00587         RXRECCLK2            : out std_logic;
00588         TXOUTCLK1            : out std_logic;
00589         TXOUTCLK2            : out std_logic;
00590         RXLOCK               : out std_logic;
00591         TXLOCK               : out std_logic;
00592         RXCYCLELIMIT         : out std_logic;
00593         TXCYCLELIMIT         : out std_logic;
00594         RXCALFAIL            : out std_logic;
00595         TXCALFAIL            : out std_logic;
00596         RXCRCOUT             : out std_logic_vector (31 downto 0);
00597         TXCRCOUT             : out std_logic_vector (31 downto 0);
00598         RXSIGDET             : out std_logic;
00599         DRDY                 : out std_logic;
00600         DO                   : out std_logic_vector (15 downto 0);
00601         RXMCLK               : out std_logic;
00602         TX1P                 : out std_logic;
00603         TX1N                 : out std_logic;
00604         TXPCSHCLKOUT         : out std_logic;
00605         RXPCSHCLKOUT         : out std_logic;
00606         COMBUSIN             : in  std_logic_vector (15 downto 0);
00607         COMBUSOUT            : out std_logic_vector (15 downto 0)
00608         );
00609   end component;
00610 
00611 
00612   component sata_cal_block_v1_4_1
00613     generic
00614       (
00615         C_MGT_ID        : integer := 0;
00616         C_TXPOST_TAP_PD : string  := "TRUE";
00617         C_RXDIGRX       : string  := "FALSE"
00618         );
00619     port
00620       (
00621         -- User DRP Interface (destination/slave interface)
00622         USER_DO            : out std_logic_vector(15 downto 0);
00623         USER_DI            : in  std_logic_vector(15 downto 0);
00624         USER_DADDR         : in  std_logic_vector(7 downto 0);
00625         USER_DEN           : in  std_logic;
00626         USER_DWE           : in  std_logic;
00627         USER_DRDY          : out std_logic;
00628         -- MGT DRP Interface (source/master interface)
00629         GT_DO              : out std_logic_vector(15 downto 0);
00630         GT_DI              : in  std_logic_vector(15 downto 0);
00631         GT_DADDR           : out std_logic_vector(7 downto 0);
00632         GT_DEN             : out std_logic;
00633         GT_DWE             : out std_logic;
00634         GT_DRDY            : in  std_logic;
00635         -- Calibration Block Active and Disable Signals (legacy)
00636         ACTIVE             : out std_logic;
00637         -- User side MGT Pass through Signals
00638         USER_LOOPBACK      : in  std_logic_vector(1 downto 0);
00639         USER_TXENC8B10BUSE : in  std_logic;
00640         USER_TXBYPASS8B10B : in  std_logic_vector(7 downto 0);
00641         -- GT side MGT Pass through Signals
00642         GT_LOOPBACK        : out std_logic_vector(1 downto 0);
00643         GT_TXENC8B10BUSE   : out std_logic;
00644         GT_TXBYPASS8B10B   : out std_logic_vector(7 downto 0);
00645         -- Signal Detect Ports
00646         TX_SIGNAL_DETECT   : in  std_logic;
00647         RX_SIGNAL_DETECT   : in  std_logic;
00648         -- Clock and Reset
00649         DCLK               : in  std_logic;
00650         RESET              : in  std_logic
00651         );
00652   end component;
00653 
00654 --********************************* Main Body of Code****************************
00655 begin
00656 
00657   ---------------------------  Static signal Assigments ----------------------   
00658   tied_to_ground_i     <= '0';
00659   tied_to_ground_vec_i <= (others => '0');
00660   tied_to_vcc_i        <= '1';
00661 
00662   --_________________________________________________________________________
00663   --_________________________________________________________________________
00664   --MGT0  (X0Y0)
00665   --------------------------- GT11 Instantiations  ---------------------------   
00666   MGT0 : GT11
00667     generic map
00668     (
00669       ---------- RocketIO MGT 64B66B Block Sync State Machine Attributes --------- 
00670       SH_CNT_MAX              => 64,
00671       SH_INVALID_CNT_MAX      => 16,
00672       ----------------------- RocketIO MGT Alignment Atrributes ------------------   
00673       ALIGN_COMMA_WORD        => 4,
00674       COMMA_10B_MASK          => x"3ff",
00675       COMMA32                 => false,
00676       DEC_MCOMMA_DETECT       => true,
00677       DEC_PCOMMA_DETECT       => true,
00678       DEC_VALID_COMMA_ONLY    => true,
00679       MCOMMA_32B_VALUE        => x"0000017c",
00680       MCOMMA_DETECT           => true,
00681       PCOMMA_32B_VALUE        => x"00000283",
00682       PCOMMA_DETECT           => true,
00683       PCS_BIT_SLIP            => false,
00684       ---- RocketIO MGT Atrributes Common to Clk Correction & Channel Bonding ----   
00685       CCCB_ARBITRATOR_DISABLE => false,
00686       CLK_COR_8B10B_DE        => true,
00687       ------------------- RocketIO MGT Channel Bonding Atrributes ----------------   
00688       CHAN_BOND_LIMIT         => 16,
00689       CHAN_BOND_MODE          => "NONE",
00690       CHAN_BOND_ONE_SHOT      => false,
00691       CHAN_BOND_SEQ_1_1       => "00000000000",
00692       CHAN_BOND_SEQ_1_2       => "00000000000",
00693       CHAN_BOND_SEQ_1_3       => "00000000000",
00694       CHAN_BOND_SEQ_1_4       => "00000000000",
00695       CHAN_BOND_SEQ_1_MASK    => "1110",
00696       CHAN_BOND_SEQ_2_1       => "00000000000",
00697       CHAN_BOND_SEQ_2_2       => "00000000000",
00698       CHAN_BOND_SEQ_2_3       => "00000000000",
00699       CHAN_BOND_SEQ_2_4       => "00000000000",
00700       CHAN_BOND_SEQ_2_MASK    => "1111",
00701       CHAN_BOND_SEQ_2_USE     => false,
00702       CHAN_BOND_SEQ_LEN       => 1,
00703       ------------------ RocketIO MGT Clock Correction Atrributes ----------------   
00704       CLK_COR_MAX_LAT         => 40,
00705       CLK_COR_MIN_LAT         => 28,
00706       CLK_COR_SEQ_1_1         => "00101111100",
00707       CLK_COR_SEQ_1_2         => "00010010101",
00708       CLK_COR_SEQ_1_3         => "00010110101",
00709       CLK_COR_SEQ_1_4         => "00010110101",
00710       CLK_COR_SEQ_1_MASK      => "0000",
00711       CLK_COR_SEQ_2_1         => "00110111100",
00712       CLK_COR_SEQ_2_2         => "00001001010",
00713       CLK_COR_SEQ_2_3         => "00001001010",
00714       CLK_COR_SEQ_2_4         => "00001111011",
00715       CLK_COR_SEQ_2_MASK      => "0000",
00716       CLK_COR_SEQ_2_USE       => true,
00717       CLK_COR_SEQ_DROP        => false,
00718       CLK_COR_SEQ_LEN         => 4,
00719       CLK_CORRECT_USE         => false,
00720       ---------------------- RocketIO MGT Clocking Atrributes --------------------      
00721       RX_CLOCK_DIVIDER        => "11",
00722       RXASYNCDIVIDE           => "10",
00723       RXCLK0_FORCE_PMACLK     => false,
00724       RXCLKMODE               => "000011",
00725       RXOUTDIV2SEL            => 2,
00726       RXPLLNDIVSEL            => 20,
00727       RXPMACLKSEL             => "REFCLK1",
00728       RXRECCLK1_USE_SYNC      => false,
00729       RXUSRDIVISOR            => 1,
00730       TX_CLOCK_DIVIDER        => "11",
00731       TXABPMACLKSEL           => "REFCLK1",
00732       TXASYNCDIVIDE           => "10",
00733       TXCLK0_FORCE_PMACLK     => false,
00734       TXCLKMODE               => "0100",
00735       TXOUTCLK1_USE_SYNC      => false,
00736       TXOUTDIV2SEL            => 2,
00737       TXPHASESEL              => true,
00738       TXPLLNDIVSEL            => 20,
00739       -------------------------- RocketIO MGT CRC Atrributes ---------------------   
00740       RXCRCCLOCKDOUBLE        => false,
00741       RXCRCENABLE             => true,
00742       RXCRCINITVAL            => x"52325032",
00743       RXCRCINVERTGEN          => false,
00744       RXCRCSAMECLOCK          => true,
00745       TXCRCCLOCKDOUBLE        => false,
00746       TXCRCENABLE             => true,
00747       TXCRCINITVAL            => x"52325032" ,
00748       TXCRCINVERTGEN          => false,
00749       TXCRCSAMECLOCK          => true,
00750       --------------------- RocketIO MGT Data Path Atrributes --------------------   
00751       RXDATA_SEL              => "11",
00752       TXDATA_SEL              => "10",
00753       ---------------- RocketIO MGT Digital Receiver Attributes ------------------   
00754       DIGRX_FWDCLK            => "00",
00755       DIGRX_SYNC_MODE         => true,
00756       ENABLE_DCDR             => false,
00757       RXBY_32                 => false,
00758       RXDIGRESET              => false,
00759       RXDIGRX                 => false,
00760       SAMPLE_8X               => false,
00761       ----------------- Rocket IO MGT Miscellaneous Attributes ------------------     
00762       GT11_MODE               => MGT0_GT11_MODE_P ,
00763       OPPOSITE_SELECT         => false,
00764       PMA_BIT_SLIP            => false,
00765       REPEATER                => false,
00766       RX_BUFFER_USE           => false,
00767       RXCDRLOS                => "000110",
00768       RXDCCOUPLE              => false,
00769       RXFDCAL_CLOCK_DIVIDE    => "NONE",
00770       TX_BUFFER_USE           => false,
00771       TXFDCAL_CLOCK_DIVIDE    => "NONE",
00772       TXSLEWRATE              => true,
00773       ----------------- Rocket IO MGT Preemphasis and Equalization --------------
00774       RXAFEEQ                 => "000000000",
00775       RXEQ                    => x"4000000000000000" ,
00776       TXDAT_PRDRV_DAC         => "111",
00777       TXDAT_TAP_DAC           => "10110",
00778       TXHIGHSIGNALEN          => true,
00779       TXPOST_PRDRV_DAC        => "111",
00780       TXPOST_TAP_DAC          => "00001",
00781       TXPOST_TAP_PD           => true,                 --serial loopback
00782       TXPRE_PRDRV_DAC         => "111",
00783       TXPRE_TAP_DAC           => "00000",
00784       TXPRE_TAP_PD            => true,
00785       ----------------------- Restricted RocketIO MGT Attributes -------------------  
00786       ---Note : THE FOLLOWING ATTRIBUTES ARE RESTRICTED. PLEASE DO NOT EDIT.
00787       ----------------------------- Restricted: Biasing -------------------------
00788       BANDGAPSEL              => false,
00789       BIASRESSEL              => false,
00790       IREFBIASMODE            => "11",
00791       PMAIREFTRIM             => "0111",
00792       PMAVREFTRIM             => "0111",
00793       TXAREFBIASSEL           => true,
00794       TXTERMTRIM              => "1100",
00795       VREFBIASMODE            => "11",
00796       ---------------- Restricted: Frequency Detector and Calibration -----------  
00797       CYCLE_LIMIT_SEL         => "00",
00798       FDET_HYS_CAL            => "010",
00799       FDET_HYS_SEL            => "100",
00800       FDET_LCK_CAL            => "101",
00801       FDET_LCK_SEL            => "001",
00802       LOOPCAL_WAIT            => "00",
00803       RXCYCLE_LIMIT_SEL       => "00",
00804       RXFDET_HYS_CAL          => "010",
00805       RXFDET_HYS_SEL          => "100",
00806       RXFDET_LCK_CAL          => "101",
00807       RXFDET_LCK_SEL          => "001",
00808       RXLOOPCAL_WAIT          => "00",
00809       RXSLOWDOWN_CAL          => "00",
00810       SLOWDOWN_CAL            => "00",
00811       --------------------------- Restricted: PLL Settings ---------------------
00812       PMACLKENABLE            => true,
00813       PMACOREPWRENABLE        => true,
00814       PMAVBGCTRL              => "00000",
00815       RXACTST                 => false,
00816       RXAFETST                => false,
00817       RXCMADJ                 => "01",
00818       RXCPSEL                 => true,
00819       RXCPTST                 => false,
00820       RXCTRL1                 => x"200",
00821       RXFECONTROL1            => "00",
00822       RXFECONTROL2            => "000",
00823       RXFETUNE                => "01",
00824       RXLKADJ                 => "00000",
00825       RXLOOPFILT              => "1111",
00826       RXPDDTST                => true,
00827       RXRCPADJ                => "011",
00828       RXRIBADJ                => "11",
00829       RXVCO_CTRL_ENABLE       => true,
00830       RXVCODAC_INIT           => "0000101001",
00831       TXCPSEL                 => true,
00832       TXCTRL1                 => x"200",
00833       TXLOOPFILT              => "1101",
00834       VCO_CTRL_ENABLE         => true,
00835       VCODAC_INIT             => "0000101001",
00836       --------------------------- Restricted: Powerdowns ------------------------  
00837       POWER_ENABLE            => true,
00838       RXAFEPD                 => false,
00839       RXAPD                   => false,
00840       RXLKAPD                 => false,
00841       RXPD                    => false,
00842       RXRCPPD                 => false,
00843       RXRPDPD                 => false,
00844       RXRSDPD                 => false,
00845       TXAPD                   => false,
00846       TXDIGPD                 => false,
00847       TXLVLSHFTPD             => false,
00848       TXPD                    => false
00849       )
00850     port map
00851     (
00852       ------------------------------- CRC Ports ------------------------------  
00853       RXCRCCLK                   => MGT_RXCRCCLK_IN,
00854       RXCRCDATAVALID             => MGT0_RXCRCDATAVALID_IN,
00855       RXCRCDATAWIDTH             => "011",             --32 bit data
00856       RXCRCIN(63 downto 32)      => MGT0_RXCRCIN_IN,
00857       RXCRCIN(31 downto 0)       => tied_to_ground_vec_i(31 downto 0),
00858       RXCRCINIT                  => MGT0_RXCRCINIT_IN,
00859       RXCRCINTCLK                => MGT_RXCRCINTCLK_IN,
00860       RXCRCOUT                   => MGT0_RXCRCOUT_OUT,
00861       RXCRCPD                    => tied_to_ground_i,
00862       RXCRCRESET                  => MGT0_RXCRCRESET_IN,
00863       TXCRCCLK                    => MGT_TXCRCCLK_IN,
00864       TXCRCDATAVALID             => MGT0_TXCRCDATAVALID_IN,
00865       TXCRCDATAWIDTH             => "011",             --32 bit data
00866       TXCRCIN(63 downto 32)      => MGT0_TXDATA_IN,
00867       TXCRCIN(31 downto 0)       => tied_to_ground_vec_i(31 downto 0),
00868       TXCRCINIT                   => MGT0_TXCRCINIT_IN,
00869       TXCRCINTCLK                 => MGT_TXCRCINTCLK_IN,
00870       TXCRCOUT                    => MGT0_TXCRCOUT_OUT,
00871       TXCRCPD                     => tied_to_ground_i,
00872       TXCRCRESET                  => MGT0_TXCRCRESET_IN,
00873       ---------------------------- Calibration Ports ------------------------   
00874       RXCALFAIL                  => open,
00875       RXCYCLELIMIT               => open,
00876       TXCALFAIL                  => open,
00877       TXCYCLELIMIT               => open,
00878       ------------------------------ Serial Ports ----------------------------   
00879       RX1N                       => MGT0_RX1N_IN,
00880       RX1P                       => MGT0_RX1P_IN,
00881       TX1N                       => MGT0_TX1N_OUT,
00882       TX1P                       => MGT0_TX1P_OUT,
00883       ------------------------------- PLL Lock -------------------------------   
00884       RXLOCK                     => MGT0_rxlock_i,
00885       TXLOCK                     => MGT0_txlock_i,
00886       -------------------------------- Resets -------------------------------  
00887       RXPMARESET                 => MGT0_rxpmareset_i,
00888       RXRESET                    => MGT0_RXRESET_IN,
00889       TXPMARESET                 => MGT0_txpmareset_i,
00890       TXRESET                     => MGT0_TXRESET_IN,
00891       ---------------------------- Synchronization ---------------------------   
00892       RXSYNC                     => MGT0_RXSYNC_IN,
00893       TXSYNC                     => MGT0_TXSYNC_IN,
00894       ---------------------------- Out of Band Signalling -------------------   
00895       RXSIGDET                   => MGT0_RXSIGDET_OUT,
00896       TXENOOB                     => MGT0_TXENOOB_IN,
00897       -------------------------------- Status --------------------------------   
00898       RXBUFERR                    => open,
00899       RXCLKSTABLE                => MGT0_RXCLKSTABLE_IN,
00900       RXSTATUS                    => MGT0_RXSTATUS_OUT,
00901       TXBUFERR                    => open,
00902       TXCLKSTABLE                 => MGT0_TXCLKSTABLE_IN,
00903       ---------------------------- Polarity Control Ports -------------------- 
00904       RXPOLARITY                  => MGT0_RXPOLARITY_IN,
00905       TXINHIBIT                  => MGT0_TXINHIBIT_IN,
00906       TXPOLARITY                 => MGT0_TXPOLARITY_IN,
00907       ------------------------------- Channel Bonding Ports ------------------   
00908       CHBONDI                     => tied_to_ground_vec_i(4 downto 0),
00909       CHBONDO                     => mgt0_chbondo_i,
00910       ENCHANSYNC                 => tied_to_ground_i,
00911       ---------------------------- 64B66B Blocks Use Ports -------------------   
00912       RXBLOCKSYNC64B66BUSE       => tied_to_ground_i,
00913       RXDEC64B66BUSE             => tied_to_ground_i,
00914       RXDESCRAM64B66BUSE         => tied_to_ground_i,
00915       RXIGNOREBTF                 => tied_to_ground_i,
00916       TXENC64B66BUSE              => tied_to_ground_i,
00917       TXGEARBOX64B66BUSE         => tied_to_ground_i,
00918       TXSCRAM64B66BUSE           => tied_to_ground_i,
00919       ---------------------------- 8B10B Blocks Use Ports --------------------   
00920       RXDEC8B10BUSE              => tied_to_vcc_i,
00921       TXBYPASS8B10B              => mgt0_txbypass8b10b_i,
00922       TXENC8B10BUSE              => mgt0_txenc8b10buse_i,
00923       ------------------------------ Transmit Control Ports ------------------   
00924       TXCHARDISPMODE(7 downto 4) => tied_to_ground_vec_i(3 downto 0),
00925       TXCHARDISPMODE(3 downto 0) => MGT0_TXCHARDISPMODE_IN,
00926       TXCHARDISPVAL(7 downto 4)  => tied_to_ground_vec_i(3 downto 0),
00927       TXCHARDISPVAL(3 downto 0)  => MGT0_TXCHARDISPVAL_IN,
00928       TXCHARISK(7 downto 4)      => tied_to_ground_vec_i(3 downto 0),
00929       TXCHARISK(3 downto 0)      => MGT0_TXCHARISK_IN,
00930       TXKERR(7 downto 4)         => mgt0_txkerr_out_float_i,
00931       TXKERR(3 downto 0)         => MGT0_TXKERR_OUT,
00932       TXRUNDISP(7 downto 4)      => mgt0_txrundisp_out_float_i,
00933       TXRUNDISP(3 downto 0)      => MGT0_TXRUNDISP_OUT,
00934       ------------------------------ Receive Control Ports -------------------   
00935       RXCHARISCOMMA(7 downto 4)  => mgt0_rxchariscomma_out_float_i,
00936       RXCHARISCOMMA(3 downto 0)  => MGT0_RXCHARISCOMMA_OUT,
00937       RXCHARISK(7 downto 4)      => mgt0_rxcharisk_out_float_i,
00938       RXCHARISK(3 downto 0)      => MGT0_RXCHARISK_OUT,
00939       RXDISPERR(7 downto 4)      => mgt0_rxdisperr_out_float_i,
00940       RXDISPERR(3 downto 0)      => MGT0_RXDISPERR_OUT,
00941       RXNOTINTABLE(7 downto 4)   => mgt0_rxnotintable_out_float_i,
00942       RXNOTINTABLE(3 downto 0)   => MGT0_RXNOTINTABLE_OUT,
00943       RXRUNDISP(7 downto 4)      => mgt0_rxrundisp_out_float_i,
00944       RXRUNDISP(3 downto 0)      => MGT0_RXRUNDISP_OUT,
00945       ------------------------------- Serdes Alignment -----------------------  
00946       ENMCOMMAALIGN              => MGT0_ENMCOMMAALIGN_IN,
00947       ENPCOMMAALIGN              => MGT0_ENPCOMMAALIGN_IN,
00948       RXCOMMADET                  => MGT0_RXCOMMADET_OUT,
00949       RXCOMMADETUSE              => RXCOMMADETUSE0_IN,
00950       RXLOSSOFSYNC               => open,
00951       RXREALIGN                   => MGT0_RXREALIGN_OUT,
00952       RXSLIDE                     => tied_to_ground_i,
00953       ----------- Data Width Settings - Internal and fabric interface -------- 
00954       RXDATAWIDTH                 => RXDATAWIDTH_P,     --parameter
00955       RXINTDATAWIDTH             => RXINTDATAWIDTH_P,  --parameter 
00956       TXDATAWIDTH                 => TXDATAWIDTH_P,     --parameter
00957       TXINTDATAWIDTH             => TXINTDATAWIDTH_P,  --parameter 
00958       ------------------------------- Data Ports -----------------------------    
00959       RXDATA(63 downto 32)       => mgt0_rxdata_out_float_i,
00960       RXDATA(31 downto 0)        => MGT0_RXDATA_OUT,
00961       TXDATA(63 downto 32)       => tied_to_ground_vec_i(31 downto 0),
00962       TXDATA(31 downto 0)        => MGT0_TXDATA_IN,
00963       ------------------------------- User Clocks -----------------------------   
00964       RXMCLK                     => open,
00965       RXPCSHCLKOUT               => open,
00966       RXRECCLK1                  => MGT0_RXRECCLK1_OUT,
00967       RXRECCLK2                   => MGT0_rxrecclk2_i,
00968       RXUSRCLK                    => tied_to_ground_i,
00969       RXUSRCLK2                  => MGT0_RXUSRCLK2_IN,
00970       TXOUTCLK1                  => MGT0_txoutclk1_i,
00971       TXOUTCLK2                  => MGT0_TXOUTCLK2_OUT,
00972       TXPCSHCLKOUT                => open,
00973       TXUSRCLK                    => tied_to_ground_i,
00974       TXUSRCLK2                   => MGT0_TXUSRCLK2_IN,
00975       ---------------------------- Reference Clocks --------------------------   
00976       GREFCLK                    => tied_to_ground_i,
00977       REFCLK1                    => MGT0_REFCLK1_IN,
00978       REFCLK2                    => tied_to_ground_i,
00979       ---------------------------- Powerdown and Loopback Ports --------------  
00980       LOOPBACK                    => MGT0_loopback_i,
00981       POWERDOWN                  => MGT0_POWERDOWN_IN,
00982       ------------------- Dynamic Reconfiguration Port (DRP) ------------------
00983       DADDR                      => MGT0_daddr_i,
00984       DCLK                        => MGT0_DCLK_IN,
00985       DEN                        => MGT0_den_i,
00986       DI                          => MGT0_di_i,
00987       DO                          => MGT0_do_i,
00988       DRDY                        => MGT0_drdy_i,
00989       DWE                         => MGT0_dwe_i,
00990       --------------------- MGT Tile Communication Ports ------------------       
00991       COMBUSIN                   => MGT0_COMBUSIN_IN,
00992       COMBUSOUT                  => MGT0_COMBUSOUT_OUT
00993       );
00994 
00995   ------------------------------- Calibration Block --------------------------
00996 
00997   -- Some signals are intercepted by different versions of the calblock. Here, we simply connect them
00998   MGT0_rxpmareset_i  <= MGT0_RXPMARESET_IN;
00999   MGT0_RXLOCK_OUT    <= MGT0_rxlock_i;
01000   MGT0_TXLOCK_OUT    <= MGT0_txlock_i;
01001   MGT0_txpmareset_i  <= MGT0_TXPMARESET_IN;
01002   MGT0_RXRECCLK2_OUT <= mgt0_rxrecclk2_i;
01003   MGT0_TXOUTCLK1_OUT <= mgt0_txoutclk1_i;
01004 
01005 
01006   MGT0_CAL_BLOCK : sata_cal_block_v1_4_1
01007     generic map
01008     (
01009       C_MGT_ID        => MGT0_MGT_ID_P,  -- 0 = MGTA | 1 = MGTB 
01010       C_TXPOST_TAP_PD => "TRUE",         -- Default POST TAP PD
01011       C_RXDIGRX       => "FALSE"          -- Default RXDIGRX
01012       )
01013     port map
01014     (
01015       -- User DRP Interface (destination/slave interface)
01016       USER_DO                         => MGT0_DO_OUT,
01017       USER_DI                        => MGT0_DI_IN,
01018       USER_DADDR                     => MGT0_DADDR_IN,
01019       USER_DEN                       => MGT0_DEN_IN,
01020       USER_DWE                       => MGT0_DWE_IN ,
01021       USER_DRDY                      => MGT0_DRDY_OUT,
01022       -- MGT DRP Interface (source/master interface)
01023       GT_DO                          => mgt0_di_i ,
01024       GT_DI                          => mgt0_do_i,
01025       GT_DADDR                       => mgt0_daddr_i,
01026       GT_DEN                         => mgt0_den_i,
01027       GT_DWE                         => mgt0_dwe_i,
01028       GT_DRDY                        => mgt0_drdy_i,
01029       -- Calibration Block Active and Disable Signals 
01030       ACTIVE                         => MGT0_ACTIVE_OUT,
01031       -- User side MGT Pass through Signals
01032       USER_LOOPBACK                   => MGT0_LOOPBACK_IN,
01033       USER_TXENC8B10BUSE             => tied_to_vcc_i,
01034       USER_TXBYPASS8B10B(7 downto 4) => tied_to_ground_vec_i(3 downto 0),
01035       USER_TXBYPASS8B10B(3 downto 0) => MGT0_TXBYPASS8B10B_IN,
01036       -- GT side MGT Pass through Signals
01037       GT_LOOPBACK                    => mgt0_loopback_i,
01038       GT_TXENC8B10BUSE               => mgt0_txenc8b10buse_i,
01039       GT_TXBYPASS8B10B               => mgt0_txbypass8b10b_i,
01040       -- Signal Detect Ports
01041       TX_SIGNAL_DETECT               => MGT0_TX_SIGNAL_DETECT_IN,
01042       RX_SIGNAL_DETECT               => MGT0_RX_SIGNAL_DETECT_IN,
01043       -- Clock and Reset
01044       DCLK                           => MGT0_DCLK_IN,
01045       RESET                           => MGT0_DRP_RESET_IN
01046       );
01047 
01048   --_________________________________________________________________________
01049   --_________________________________________________________________________
01050   --MGT1  (X0Y1)
01051   --------------------------- GT11 Instantiations  ---------------------------
01052 
01053   MGT1 : GT11
01054     generic map
01055     (
01056       ---------- RocketIO MGT 64B66B Block Sync State Machine Attributes --------- 
01057       SH_CNT_MAX              => 64,
01058       SH_INVALID_CNT_MAX      => 16,
01059       ----------------------- RocketIO MGT Alignment Atrributes ------------------   
01060       ALIGN_COMMA_WORD        => 4,
01061       COMMA_10B_MASK          => x"3ff",
01062       COMMA32                 => false,
01063       DEC_MCOMMA_DETECT       => true,
01064       DEC_PCOMMA_DETECT       => true,
01065       DEC_VALID_COMMA_ONLY    => true,
01066       MCOMMA_32B_VALUE        => x"0000017c",
01067       MCOMMA_DETECT           => true,
01068       PCOMMA_32B_VALUE        => x"00000283",
01069       PCOMMA_DETECT           => true,
01070       PCS_BIT_SLIP            => false,
01071       ---- RocketIO MGT Atrributes Common to Clk Correction & Channel Bonding ----   
01072       CCCB_ARBITRATOR_DISABLE => false,
01073       CLK_COR_8B10B_DE        => true,
01074       ------------------- RocketIO MGT Channel Bonding Atrributes ----------------   
01075       CHAN_BOND_LIMIT         => 16,
01076       CHAN_BOND_MODE          => "NONE",
01077       CHAN_BOND_ONE_SHOT      => false,
01078       CHAN_BOND_SEQ_1_1       => "00000000000",
01079       CHAN_BOND_SEQ_1_2       => "00000000000",
01080       CHAN_BOND_SEQ_1_3       => "00000000000",
01081       CHAN_BOND_SEQ_1_4       => "00000000000",
01082       CHAN_BOND_SEQ_1_MASK    => "1110",
01083       CHAN_BOND_SEQ_2_1       => "00000000000",
01084       CHAN_BOND_SEQ_2_2       => "00000000000",
01085       CHAN_BOND_SEQ_2_3       => "00000000000",
01086       CHAN_BOND_SEQ_2_4       => "00000000000",
01087       CHAN_BOND_SEQ_2_MASK    => "1111",
01088       CHAN_BOND_SEQ_2_USE     => false,
01089       CHAN_BOND_SEQ_LEN       => 1,
01090       ------------------ RocketIO MGT Clock Correction Atrributes ----------------   
01091       CLK_COR_MAX_LAT         => 40,
01092       CLK_COR_MIN_LAT         => 28,
01093       CLK_COR_SEQ_1_1         => "00101111100",
01094       CLK_COR_SEQ_1_2         => "00010010101",
01095       CLK_COR_SEQ_1_3         => "00010110101",
01096       CLK_COR_SEQ_1_4         => "00010110101",
01097       CLK_COR_SEQ_1_MASK      => "0000",
01098       CLK_COR_SEQ_2_1         => "00110111100",
01099       CLK_COR_SEQ_2_2         => "00001001010",
01100       CLK_COR_SEQ_2_3         => "00001001010",
01101       CLK_COR_SEQ_2_4         => "00001111011",
01102       CLK_COR_SEQ_2_MASK      => "0000",
01103       CLK_COR_SEQ_2_USE       => true,
01104       CLK_COR_SEQ_DROP        => false,
01105       CLK_COR_SEQ_LEN         => 4,
01106       CLK_CORRECT_USE         => false,
01107       ---------------------- RocketIO MGT Clocking Atrributes --------------------      
01108       RX_CLOCK_DIVIDER        => "11",
01109       RXASYNCDIVIDE           => "10",
01110       RXCLK0_FORCE_PMACLK     => false,
01111       RXCLKMODE               => "000011",
01112       RXOUTDIV2SEL            => 2,
01113       RXPLLNDIVSEL            => 20,
01114       RXPMACLKSEL             => "REFCLK1",
01115       RXRECCLK1_USE_SYNC      => false,
01116       RXUSRDIVISOR            => 1,
01117       TX_CLOCK_DIVIDER        => "11",
01118       TXABPMACLKSEL           => "REFCLK1",
01119       TXASYNCDIVIDE           => "10",
01120       TXCLK0_FORCE_PMACLK     => false,
01121       TXCLKMODE               => "0100",
01122       TXOUTCLK1_USE_SYNC      => false,
01123       TXOUTDIV2SEL            => 2,
01124       TXPHASESEL              => true,
01125       TXPLLNDIVSEL            => 20,
01126       -------------------------- RocketIO MGT CRC Atrributes ---------------------   
01127       RXCRCCLOCKDOUBLE        => false,
01128       RXCRCENABLE             => true,
01129       RXCRCINITVAL            => x"52325032",
01130       RXCRCINVERTGEN          => false,
01131       RXCRCSAMECLOCK          => true,
01132       TXCRCCLOCKDOUBLE        => false,
01133       TXCRCENABLE             => true,
01134       TXCRCINITVAL            => x"52325032",
01135       TXCRCINVERTGEN          => false,
01136       TXCRCSAMECLOCK          => true,
01137       --------------------- RocketIO MGT Data Path Atrributes --------------------   
01138       RXDATA_SEL              => "11",
01139       TXDATA_SEL              => "10",
01140       ---------------- RocketIO MGT Digital Receiver Attributes ------------------   
01141       DIGRX_FWDCLK            => "00",
01142       DIGRX_SYNC_MODE         => true,
01143       ENABLE_DCDR             => false,
01144       RXBY_32                 => false,
01145       RXDIGRESET              => false,
01146       RXDIGRX                 => false,
01147       SAMPLE_8X               => false,
01148       ----------------- Rocket IO MGT Miscellaneous Attributes ------------------     
01149       GT11_MODE               => MGT1_GT11_MODE_P ,
01150       OPPOSITE_SELECT         => false,
01151       PMA_BIT_SLIP            => false,
01152       REPEATER                => false,
01153       RX_BUFFER_USE           => false,
01154       RXCDRLOS                => "000110",
01155       RXDCCOUPLE              => false,
01156       RXFDCAL_CLOCK_DIVIDE    => "NONE",
01157       TX_BUFFER_USE           => false,
01158       TXFDCAL_CLOCK_DIVIDE    => "NONE",
01159       TXSLEWRATE              => true,
01160       ----------------- Rocket IO MGT Preemphasis and Equalization --------------
01161       RXAFEEQ                 => "000000000",
01162       RXEQ                    => x"4000000000000000" ,
01163       TXDAT_PRDRV_DAC         => "111",
01164       TXDAT_TAP_DAC           => "10110",
01165       TXHIGHSIGNALEN          => true,
01166       TXPOST_PRDRV_DAC        => "111",
01167       TXPOST_TAP_DAC          => "00001",
01168       TXPOST_TAP_PD           => true,                 --serial loopback
01169       TXPRE_PRDRV_DAC         => "111",
01170       TXPRE_TAP_DAC           => "00000",
01171       TXPRE_TAP_PD            => true,
01172       ----------------------- Restricted RocketIO MGT Attributes -------------------  
01173       ---Note : THE FOLLOWING ATTRIBUTES ARE RESTRICTED. PLEASE DO NOT EDIT.
01174       ----------------------------- Restricted: Biasing -------------------------
01175       BANDGAPSEL              => false,
01176       BIASRESSEL              => false,
01177       IREFBIASMODE            => "11",
01178       PMAIREFTRIM             => "0111",
01179       PMAVREFTRIM             => "0111",
01180       TXAREFBIASSEL           => true,
01181       TXTERMTRIM              => "1100",
01182       VREFBIASMODE            => "11",
01183       ---------------- Restricted: Frequency Detector and Calibration -----------  
01184       CYCLE_LIMIT_SEL         => "00",
01185       FDET_HYS_CAL            => "010",
01186       FDET_HYS_SEL            => "100",
01187       FDET_LCK_CAL            => "101",
01188       FDET_LCK_SEL            => "001",
01189       LOOPCAL_WAIT            => "00",
01190       RXCYCLE_LIMIT_SEL       => "00",
01191       RXFDET_HYS_CAL          => "010",
01192       RXFDET_HYS_SEL          => "100",
01193       RXFDET_LCK_CAL          => "101",
01194       RXFDET_LCK_SEL          => "001",
01195       RXLOOPCAL_WAIT          => "00",
01196       RXSLOWDOWN_CAL          => "00",
01197       SLOWDOWN_CAL            => "00",
01198       --------------------------- Restricted: PLL Settings ---------------------
01199       PMACLKENABLE            => true,
01200       PMACOREPWRENABLE        => true,
01201       PMAVBGCTRL              => "00000",
01202       RXACTST                 => false,
01203       RXAFETST                => false,
01204       RXCMADJ                 => "01",
01205       RXCPSEL                 => true,
01206       RXCPTST                 => false,
01207       RXCTRL1                 => x"200",
01208       RXFECONTROL1            => "00",
01209       RXFECONTROL2            => "000",
01210       RXFETUNE                => "01",
01211       RXLKADJ                 => "00000",
01212       RXLOOPFILT              => "1111",
01213       RXPDDTST                => true,
01214       RXRCPADJ                => "011",
01215       RXRIBADJ                => "11",
01216       RXVCO_CTRL_ENABLE       => true,
01217       RXVCODAC_INIT           => "0000101001",
01218       TXCPSEL                 => true,
01219       TXCTRL1                 => x"200",
01220       TXLOOPFILT              => "1101",
01221       VCO_CTRL_ENABLE         => true,
01222       VCODAC_INIT             => "0000101001",
01223       --------------------------- Restricted: Powerdowns ------------------------  
01224       POWER_ENABLE            => true,
01225       RXAFEPD                 => false,
01226       RXAPD                   => false,
01227       RXLKAPD                 => false,
01228       RXPD                    => false,
01229       RXRCPPD                 => false,
01230       RXRPDPD                 => false,
01231       RXRSDPD                 => false,
01232       TXAPD                   => false,
01233       TXDIGPD                 => false,
01234       TXLVLSHFTPD             => false,
01235       TXPD                    => false
01236       )
01237     port map
01238     (
01239       ------------------------------- CRC Ports ------------------------------  
01240       RXCRCCLK                   => MGT_RXCRCCLK_IN,
01241       RXCRCDATAVALID             => MGT1_RXCRCDATAVALID_IN,
01242       RXCRCDATAWIDTH             => "011",             --32 bit data
01243       RXCRCIN(63 downto 32)      => MGT1_RXCRCIN_IN,
01244       RXCRCIN(31 downto 0)       => tied_to_ground_vec_i(31 downto 0),
01245       RXCRCINIT                  => MGT1_RXCRCINIT_IN,
01246       RXCRCINTCLK                => MGT_RXCRCINTCLK_IN,
01247       RXCRCOUT                    => MGT1_RXCRCOUT_OUT,
01248       RXCRCPD                    => tied_to_ground_i,
01249       RXCRCRESET                  => MGT1_RXCRCRESET_IN,
01250       TXCRCCLK                    => MGT_TXCRCCLK_IN,
01251       TXCRCDATAVALID             => MGT1_TXCRCDATAVALID_IN,
01252       TXCRCDATAWIDTH             => "011",             --32 bit data
01253       TXCRCIN(63 downto 32)      => MGT1_TXDATA_IN,
01254       TXCRCIN(31 downto 0)       => tied_to_ground_vec_i(31 downto 0),
01255       TXCRCINIT                   => MGT1_TXCRCINIT_IN,
01256       TXCRCINTCLK                 => MGT_TXCRCINTCLK_IN,
01257       TXCRCOUT                    => MGT1_TXCRCOUT_OUT,
01258       TXCRCPD                     => tied_to_ground_i,
01259       TXCRCRESET                  => MGT1_TXCRCRESET_IN,
01260       ---------------------------- Calibration Ports ------------------------   
01261       RXCALFAIL                  => open,
01262       RXCYCLELIMIT               => open,
01263       TXCALFAIL                  => open,
01264       TXCYCLELIMIT               => open,
01265       ------------------------------ Serial Ports ----------------------------   
01266       RX1N                       => MGT1_RX1N_IN,
01267       RX1P                       => MGT1_RX1P_IN,
01268       TX1N                       => MGT1_TX1N_OUT,
01269       TX1P                       => MGT1_TX1P_OUT,
01270       ------------------------------- PLL Lock -------------------------------   
01271       RXLOCK                     => MGT1_rxlock_i,
01272       TXLOCK                     => MGT1_txlock_i,
01273       -------------------------------- Resets -------------------------------  
01274       RXPMARESET                 => MGT1_rxpmareset_i,
01275       RXRESET                    => MGT1_RXRESET_IN,
01276       TXPMARESET                  => MGT1_txpmareset_i,
01277       TXRESET                    => MGT1_TXRESET_IN,
01278       ---------------------------- Synchronization ---------------------------   
01279       RXSYNC                      => MGT1_RXSYNC_IN,
01280       TXSYNC                      => MGT1_TXSYNC_IN,
01281       ---------------------------- Out of Band Signalling -------------------   
01282       RXSIGDET                    => MGT1_RXSIGDET_OUT,
01283       TXENOOB                     => MGT1_TXENOOB_IN,
01284       -------------------------------- Status --------------------------------   
01285       RXBUFERR                    => open,
01286       RXCLKSTABLE                 => MGT1_RXCLKSTABLE_IN,
01287       RXSTATUS                    => MGT1_RXSTATUS_OUT,
01288       TXBUFERR                    => open,
01289       TXCLKSTABLE                 => MGT1_TXCLKSTABLE_IN,
01290       ---------------------------- Polarity Control Ports -------------------- 
01291       RXPOLARITY                  => MGT1_RXPOLARITY_IN,
01292       TXINHIBIT                   => MGT1_TXINHIBIT_IN,
01293       TXPOLARITY                  => MGT1_TXPOLARITY_IN,
01294       ------------------------------- Channel Bonding Ports ------------------   
01295       CHBONDI                     => tied_to_ground_vec_i(4 downto 0),
01296       CHBONDO                     => mgt1_chbondo_i,
01297       ENCHANSYNC                  => tied_to_ground_i,
01298       ---------------------------- 64B66B Blocks Use Ports -------------------   
01299       RXBLOCKSYNC64B66BUSE       => tied_to_ground_i,
01300       RXDEC64B66BUSE             => tied_to_ground_i,
01301       RXDESCRAM64B66BUSE         => tied_to_ground_i,
01302       RXIGNOREBTF                 => tied_to_ground_i,
01303       TXENC64B66BUSE             => tied_to_ground_i,
01304       TXGEARBOX64B66BUSE         => tied_to_ground_i,
01305       TXSCRAM64B66BUSE           => tied_to_ground_i,
01306       ---------------------------- 8B10B Blocks Use Ports --------------------   
01307       RXDEC8B10BUSE              => tied_to_vcc_i,
01308       TXBYPASS8B10B              => mgt1_txbypass8b10b_i,
01309       TXENC8B10BUSE              => mgt1_txenc8b10buse_i,
01310       ------------------------------ Transmit Control Ports ------------------   
01311       TXCHARDISPMODE(7 downto 4) => tied_to_ground_vec_i(3 downto 0),
01312       TXCHARDISPMODE(3 downto 0) => MGT1_TXCHARDISPMODE_IN,
01313       TXCHARDISPVAL(7 downto 4)  => tied_to_ground_vec_i(3 downto 0),
01314       TXCHARDISPVAL(3 downto 0)  => MGT1_TXCHARDISPVAL_IN,
01315       TXCHARISK(7 downto 4)      => tied_to_ground_vec_i(3 downto 0),
01316       TXCHARISK(3 downto 0)      => MGT1_TXCHARISK_IN,
01317       TXKERR(7 downto 4)         => mgt1_txkerr_out_float_i,
01318       TXKERR(3 downto 0)         => MGT1_TXKERR_OUT,
01319       TXRUNDISP(7 downto 4)      => mgt1_txrundisp_out_float_i,
01320       TXRUNDISP(3 downto 0)      => MGT1_TXRUNDISP_OUT,
01321       ------------------------------ Receive Control Ports -------------------   
01322       RXCHARISCOMMA(7 downto 4)  => mgt1_rxchariscomma_out_float_i,
01323       RXCHARISCOMMA(3 downto 0)  => MGT1_RXCHARISCOMMA_OUT,
01324       RXCHARISK(7 downto 4)      => mgt1_rxcharisk_out_float_i,
01325       RXCHARISK(3 downto 0)      => MGT1_RXCHARISK_OUT,
01326       RXDISPERR(7 downto 4)      => mgt1_rxdisperr_out_float_i,
01327       RXDISPERR(3 downto 0)      => MGT1_RXDISPERR_OUT,
01328       RXNOTINTABLE(7 downto 4)   => mgt1_rxnotintable_out_float_i,
01329       RXNOTINTABLE(3 downto 0)   => MGT1_RXNOTINTABLE_OUT,
01330       RXRUNDISP(7 downto 4)      => mgt1_rxrundisp_out_float_i,
01331       RXRUNDISP(3 downto 0)      => MGT1_RXRUNDISP_OUT,
01332       ------------------------------- Serdes Alignment -----------------------  
01333       ENMCOMMAALIGN              => MGT1_ENMCOMMAALIGN_IN,
01334       ENPCOMMAALIGN              => MGT1_ENPCOMMAALIGN_IN,
01335       RXCOMMADET                  => MGT1_RXCOMMADET_OUT,
01336       RXCOMMADETUSE              => RXCOMMADETUSE1_IN,
01337       RXLOSSOFSYNC               => open,
01338       RXREALIGN                   => MGT1_RXREALIGN_OUT,
01339       RXSLIDE                    => tied_to_ground_i,
01340       ----------- Data Width Settings - Internal and fabric interface -------- 
01341       RXDATAWIDTH                => RXDATAWIDTH_P,     --parameter
01342       RXINTDATAWIDTH             => RXINTDATAWIDTH_P,  --parameter 
01343       TXDATAWIDTH                 => TXDATAWIDTH_P,     --parameter
01344       TXINTDATAWIDTH             => TXINTDATAWIDTH_P,  --parameter 
01345       ------------------------------- Data Ports -----------------------------    
01346       RXDATA(63 downto 32)       => mgt1_rxdata_out_float_i,
01347       RXDATA(31 downto 0)        => MGT1_RXDATA_OUT,
01348       TXDATA(63 downto 32)       => tied_to_ground_vec_i(31 downto 0),
01349       TXDATA(31 downto 0)        => MGT1_TXDATA_IN,
01350       ------------------------------- User Clocks -----------------------------   
01351       RXMCLK                     => open,
01352       RXPCSHCLKOUT               => open,
01353       RXRECCLK1                  => MGT1_RXRECCLK1_OUT,
01354       RXRECCLK2                  => MGT1_rxrecclk2_i,
01355       RXUSRCLK                    => tied_to_ground_i,
01356       RXUSRCLK2                   => MGT1_RXUSRCLK2_IN,
01357       TXOUTCLK1                   => MGT1_txoutclk1_i,
01358       TXOUTCLK2                   => MGT1_TXOUTCLK2_OUT,
01359       TXPCSHCLKOUT                => open,
01360       TXUSRCLK                   => tied_to_ground_i,
01361       TXUSRCLK2                   => MGT1_TXUSRCLK2_IN,
01362       ---------------------------- Reference Clocks --------------------------   
01363       GREFCLK                     => tied_to_ground_i,
01364       REFCLK1                     => MGT1_REFCLK1_IN,
01365       REFCLK2                     => tied_to_ground_i,
01366       ---------------------------- Powerdown and Loopback Ports --------------  
01367       LOOPBACK                    => MGT1_loopback_i,
01368       POWERDOWN                  => MGT1_POWERDOWN_IN,
01369       ------------------- Dynamic Reconfiguration Port (DRP) ------------------
01370       DADDR                      => MGT1_daddr_i,
01371       DCLK                       => MGT1_DCLK_IN,
01372       DEN                        => MGT1_den_i,
01373       DI                         => MGT1_di_i,
01374       DO                         => MGT1_do_i,
01375       DRDY                       => MGT1_drdy_i,
01376       DWE                        => MGT1_dwe_i,
01377       --------------------- MGT Tile Communication Ports ------------------       
01378       COMBUSIN                   => MGT1_COMBUSIN_IN,
01379       COMBUSOUT                   => MGT1_COMBUSOUT_OUT 
01380       );
01381 
01382 
01383   ------------------------------- Calibration Block --------------------------
01384 
01385   -- Some signals are intercepted by different versions of the calblock. Here, we simply connect them
01386   MGT1_rxpmareset_i  <= MGT1_RXPMARESET_IN;
01387   MGT1_RXLOCK_OUT    <= MGT1_rxlock_i;
01388   MGT1_TXLOCK_OUT    <= MGT1_txlock_i;
01389   MGT1_txpmareset_i  <= MGT1_TXPMARESET_IN;
01390   MGT1_RXRECCLK2_OUT <= mgt1_rxrecclk2_i;
01391   MGT1_TXOUTCLK1_OUT <= mgt1_txoutclk1_i;
01392 
01393 
01394   MGT1_CAL_BLOCK : sata_cal_block_v1_4_1
01395     generic map
01396     (
01397       C_MGT_ID        => MGT1_MGT_ID_P,
01398       C_TXPOST_TAP_PD => "TRUE",
01399       C_RXDIGRX       => "FALSE"
01400       )
01401     port map
01402     (
01403       -- User DRP Interface (destination/slave interface)
01404       USER_DO                        => MGT1_DO_OUT,
01405       USER_DI                        => MGT1_DI_IN,
01406       USER_DADDR                     => MGT1_DADDR_IN,
01407       USER_DEN                        => MGT1_DEN_IN,
01408       USER_DWE                       => MGT1_DWE_IN,
01409       USER_DRDY                      => MGT1_DRDY_OUT,
01410       -- MGT DRP Interface (source/master interface)
01411       GT_DO                          => mgt1_di_i,
01412       GT_DI                          => mgt1_do_i,
01413       GT_DADDR                       => mgt1_daddr_i,
01414       GT_DEN                         => mgt1_den_i,
01415       GT_DWE                         => mgt1_dwe_i,
01416       GT_DRDY                        => mgt1_drdy_i,
01417       -- Calibration Block Active and Disable Signals 
01418       ACTIVE                         => MGT1_ACTIVE_OUT,
01419       -- User side MGT Pass through Signals
01420       USER_LOOPBACK                   => MGT1_LOOPBACK_IN,
01421       USER_TXENC8B10BUSE             => tied_to_vcc_i,
01422       USER_TXBYPASS8B10B(7 downto 4) => tied_to_ground_vec_i(3 downto 0),
01423       USER_TXBYPASS8B10B(3 downto 0) => MGT1_TXBYPASS8B10B_IN,
01424       -- GT side MGT Pass through Signals
01425       GT_LOOPBACK                     => mgt1_loopback_i,
01426       GT_TXENC8B10BUSE               => mgt1_txenc8b10buse_i,
01427       GT_TXBYPASS8B10B               => mgt1_txbypass8b10b_i,
01428       -- Signal Detect Ports
01429       TX_SIGNAL_DETECT               => MGT1_TX_SIGNAL_DETECT_IN ,
01430       RX_SIGNAL_DETECT               => MGT1_RX_SIGNAL_DETECT_IN,
01431       -- Clock and Reset
01432       DCLK                           => MGT1_DCLK_IN,
01433       RESET                           => MGT1_DRP_RESET_IN
01434       );
01435 
01436 end ROCKETIO_SATA_arc;
01437