intime.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/coin/Attic/intime.vhd,v $
--*  $Revision: 1.1.2.6 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:42 $                              *



--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;





entity intime is
  
  port (
    CLK           : in  std_logic;
    UPPER_BOUND_A : in  std_logic_vector(5 downto 0) := "101110";
    LOWER_BOUND_A : in  std_logic_vector(5 downto 0) := "010000";
    UPPER_BOUND_C : in  std_logic_vector(5 downto 0) := "101110";
    LOWER_BOUND_C : in  std_logic_vector(5 downto 0) := "010000";
    IRENA1        : in  std_logic_vector (7 downto 0);
    EWA1          : in  std_logic_vector (7 downto 0);
    HEINZ1        : in  std_logic_vector (7 downto 0);
    ANDREJ1       : in  std_logic_vector (7 downto 0);
    MARKO1        : in  std_logic_vector (7 downto 0);
    WILLIAM1      : in  std_logic_vector (7 downto 0);
    HARRIS1       : in  std_logic_vector (7 downto 0);
    HELMUT1       : in  std_logic_vector (7 downto 0);
    IRENA2        : in  std_logic_vector (7 downto 0);
    EWA2          : in  std_logic_vector (7 downto 0);
    HEINZ2        : in  std_logic_vector (7 downto 0);
    ANDREJ2       : in  std_logic_vector (7 downto 0);
    MARKO2        : in  std_logic_vector (7 downto 0);
    WILLIAM2      : in  std_logic_vector (7 downto 0);
    HARRIS2       : in  std_logic_vector (7 downto 0);
    HELMUT2       : in  std_logic_vector (7 downto 0);
    S_IRENA1      : in  std_logic;
    S_EWA1        : in  std_logic;
    S_HEINZ1      : in  std_logic;
    S_ANDREJ1     : in  std_logic;
    S_MARKO1      : in  std_logic;
    S_WILLIAM1    : in  std_logic;
    S_HARRIS1     : in  std_logic;
    S_HELMUT1     : in  std_logic;
    S_IRENA2      : in  std_logic;
    S_EWA2        : in  std_logic;
    S_HEINZ2      : in  std_logic;
    S_ANDREJ2     : in  std_logic;
    S_MARKO2      : in  std_logic;
    S_WILLIAM2    : in  std_logic;
    S_HARRIS2     : in  std_logic;
    S_HELMUT2     : in  std_logic;
    IRENA1_O      : out std_logic_vector (7 downto 0);
    EWA1_O        : out std_logic_vector (7 downto 0);
    HEINZ1_O      : out std_logic_vector (7 downto 0);
    ANDREJ1_O     : out std_logic_vector (7 downto 0);
    MARKO1_O      : out std_logic_vector (7 downto 0);
    WILLIAM1_O    : out std_logic_vector (7 downto 0);
    HARRIS1_O     : out std_logic_vector (7 downto 0);
    HELMUT1_O     : out std_logic_vector (7 downto 0);
    IRENA2_O      : out std_logic_vector (7 downto 0);
    EWA2_O        : out std_logic_vector (7 downto 0);
    HEINZ2_O      : out std_logic_vector (7 downto 0);
    ANDREJ2_O     : out std_logic_vector (7 downto 0);
    MARKO2_O      : out std_logic_vector (7 downto 0);
    WILLIAM2_O    : out std_logic_vector (7 downto 0);
    HARRIS2_O     : out std_logic_vector (7 downto 0);
    HELMUT2_O     : out std_logic_vector (7 downto 0);
    S_IRENA1_O    : out std_logic;
    S_EWA1_O      : out std_logic;
    S_HEINZ1_O    : out std_logic;
    S_ANDREJ1_O   : out std_logic;
    S_MARKO1_O    : out std_logic;
    S_WILLIAM1_O  : out std_logic;
    S_HARRIS1_O   : out std_logic;
    S_HELMUT1_O   : out std_logic;
    S_IRENA2_O    : out std_logic;
    S_EWA2_O      : out std_logic;
    S_HEINZ2_O    : out std_logic;
    S_ANDREJ2_O   : out std_logic;
    S_MARKO2_O    : out std_logic;
    S_WILLIAM2_O  : out std_logic;
    S_HARRIS2_O   : out std_logic;
    S_HELMUT2_O   : out std_logic
    );

end intime;





architecture intime_arc of intime is

--*************************** Signal Declarations *****************************
  signal hit_irena1   : std_logic                    := '0';
  signal hit_ewa1     : std_logic                    := '0';
  signal hit_heinz1   : std_logic                    := '0';
  signal hit_andrej1  : std_logic                    := '0';
  signal hit_marko1   : std_logic                    := '0';
  signal hit_william1 : std_logic                    := '0';
  signal hit_harris1  : std_logic                    := '0';
  signal hit_helmut1  : std_logic                    := '0';
  signal hit_irena2   : std_logic                    := '0';
  signal hit_ewa2     : std_logic                    := '0';
  signal hit_heinz2   : std_logic                    := '0';
  signal hit_andrej2  : std_logic                    := '0';
  signal hit_marko2   : std_logic                    := '0';
  signal hit_william2 : std_logic                    := '0';
  signal hit_harris2  : std_logic                    := '0';
  signal hit_helmut2  : std_logic                    := '0';
  signal irena1_bc    : std_logic_vector(5 downto 0) := (others => '0');
  signal ewa1_bc      : std_logic_vector(5 downto 0) := (others => '0');
  signal heinz1_bc    : std_logic_vector(5 downto 0) := (others => '0');
  signal andrej1_bc   : std_logic_vector(5 downto 0) := (others => '0');
  signal marko1_bc    : std_logic_vector(5 downto 0) := (others => '0');
  signal william1_bc  : std_logic_vector(5 downto 0) := (others => '0');
  signal harris1_bc   : std_logic_vector(5 downto 0) := (others => '0');
  signal helmut1_bc   : std_logic_vector(5 downto 0) := (others => '0');
  signal irena2_bc    : std_logic_vector(5 downto 0) := (others => '0');
  signal ewa2_bc      : std_logic_vector(5 downto 0) := (others => '0');
  signal heinz2_bc    : std_logic_vector(5 downto 0) := (others => '0');
  signal andrej2_bc   : std_logic_vector(5 downto 0) := (others => '0');
  signal marko2_bc    : std_logic_vector(5 downto 0) := (others => '0');
  signal william2_bc  : std_logic_vector(5 downto 0) := (others => '0');
  signal harris2_bc   : std_logic_vector(5 downto 0) := (others => '0');
  signal helmut2_bc   : std_logic_vector(5 downto 0) := (others => '0');
  signal irena1_xy    : std_logic_vector(5 downto 0) := (others => '0');
  signal ewa1_xy      : std_logic_vector(5 downto 0) := (others => '0');
  signal heinz1_xy    : std_logic_vector(5 downto 0) := (others => '0');
  signal andrej1_xy   : std_logic_vector(5 downto 0) := (others => '0');
  signal marko1_xy    : std_logic_vector(5 downto 0) := (others => '0');
  signal william1_xy  : std_logic_vector(5 downto 0) := (others => '0');
  signal harris1_xy   : std_logic_vector(5 downto 0) := (others => '0');
  signal helmut1_xy   : std_logic_vector(5 downto 0) := (others => '0');
  signal irena2_xy    : std_logic_vector(5 downto 0) := (others => '0');
  signal ewa2_xy      : std_logic_vector(5 downto 0) := (others => '0');
  signal heinz2_xy    : std_logic_vector(5 downto 0) := (others => '0');
  signal andrej2_xy   : std_logic_vector(5 downto 0) := (others => '0');
  signal marko2_xy    : std_logic_vector(5 downto 0) := (others => '0');
  signal william2_xy  : std_logic_vector(5 downto 0) := (others => '0');
  signal harris2_xy   : std_logic_vector(5 downto 0) := (others => '0');
  signal helmut2_xy   : std_logic_vector(5 downto 0) := (others => '0');

--************************** Component Declarations ***************************


  component timewindow
    port(
      CLK     : in  std_logic;
      UPPER   : in  std_logic_vector(5 downto 0) := "101110";
      LOWER   : in  std_logic_vector(5 downto 0) := "010000";
      VAL_IN  : in  std_logic_vector(5 downto 0);
      VAL_OUT : out std_logic_vector(5 downto 0);
      IN_TIME : out std_logic
      );
  end component;

--*************************************************************************
--*                               main code
--*************************************************************************
begin  -- intime_arc

-------------------------------------------------------------------------------
-- input assignments
-------------------------------------------------------------------------------  
  irena1_bc   <= IRENA1(5 downto 0)   when S_IRENA1 = '1'   else (others => '0');
  ewa1_bc     <= EWA1(5 downto 0)     when S_EWA1 = '1'     else (others => '0');
  heinz1_bc   <= HEINZ1(5 downto 0)   when S_HEINZ1 = '1'   else (others => '0');
  andrej1_bc  <= ANDREJ1(5 downto 0)  when S_ANDREJ1 = '1'  else (others => '0');
  marko1_bc   <= MARKO1(5 downto 0)   when S_MARKO1 = '1'   else (others => '0');
  william1_bc <= WILLIAM1(5 downto 0) when S_WILLIAM1 = '1' else (others => '0');
  harris1_bc  <= HARRIS1(5 downto 0)  when S_HARRIS1 = '1'  else (others => '0');
  helmut1_bc  <= HELMUT1(5 downto 0)  when S_HELMUT1 = '1'  else (others => '0');

  irena2_bc   <= IRENA2(5 downto 0)   when S_IRENA2 = '1'   else (others => '0');
  ewa2_bc     <= EWA2(5 downto 0)     when S_EWA2 = '1'     else (others => '0');
  heinz2_bc   <= HEINZ2(5 downto 0)   when S_HEINZ2 = '1'   else (others => '0');
  andrej2_bc  <= ANDREJ2(5 downto 0)  when S_ANDREJ2 = '1'  else (others => '0');
  marko2_bc   <= MARKO2(5 downto 0)   when S_MARKO2 = '1'   else (others => '0');
  william2_bc <= WILLIAM2(5 downto 0) when S_WILLIAM2 = '1' else (others => '0');
  harris2_bc  <= HARRIS2(5 downto 0)  when S_HARRIS2 = '1'  else (others => '0');
  helmut2_bc  <= HELMUT2(5 downto 0)  when S_HELMUT2 = '1'  else (others => '0');

-------------------------------------------------------------------------------
-- time cuts
-------------------------------------------------------------------------------  
  Irena_1 : timewindow
    port map
    (
      CLK     => CLK ,
      UPPER   => UPPER_BOUND_C,
      LOWER   => LOWER_BOUND_C,
      VAL_IN  => irena1_bc,
      VAL_OUT => irena1_xy,
      IN_TIME => hit_irena1
      );
  Irena_2 : timewindow
    port map
    (
      CLK     => CLK ,
      UPPER   => UPPER_BOUND_C,
      LOWER   => LOWER_BOUND_C,
      VAL_IN  => irena2_bc,
      VAL_OUT => irena2_xy,
      IN_TIME => hit_irena2
      );

  ewa_1 : timewindow
    port map
    (
      CLK     => CLK ,
      UPPER   => UPPER_BOUND_C,
      LOWER   => LOWER_BOUND_C,
      VAL_IN  => ewa1_bc,
      VAL_OUT => ewa1_xy,
      IN_TIME => hit_ewa1
      );
  ewa_2 : timewindow
    port map
    (
      CLK     => CLK ,
      UPPER   => UPPER_BOUND_C,
      LOWER   => LOWER_BOUND_C,
      VAL_IN  => ewa2_bc,
      VAL_OUT => ewa2_xy,
      IN_TIME => hit_ewa2
      );

  heinz_1 : timewindow
    port map
    (
      CLK     => CLK ,
      UPPER   => UPPER_BOUND_C,
      LOWER   => LOWER_BOUND_C,
      VAL_IN  => heinz1_bc,
      VAL_OUT => heinz1_xy,
      IN_TIME => hit_heinz1
      );
  heinz_2 : timewindow
    port map
    (
      CLK     => CLK ,
      UPPER   => UPPER_BOUND_C,
      LOWER   => LOWER_BOUND_C,
      VAL_IN  => heinz2_bc,
      VAL_OUT => heinz2_xy,
      IN_TIME => hit_heinz2
      );

  andrej_1 : timewindow
    port map
    (
      CLK     => CLK ,
      UPPER   => UPPER_BOUND_C,
      LOWER   => LOWER_BOUND_C,
      VAL_IN  => andrej1_bc ,
      VAL_OUT => andrej1_xy,
      IN_TIME => hit_andrej1 
      );
  andrej_2 : timewindow
    port map
    (
      CLK     => CLK ,
      UPPER   => UPPER_BOUND_C,
      LOWER   => LOWER_BOUND_C,
      VAL_IN  => andrej2_bc ,
      VAL_OUT => andrej2_xy,
      IN_TIME => hit_andrej2 
      );

  marko_1 : timewindow
    port map
    (
      CLK     => CLK ,
      UPPER   => UPPER_BOUND_A,
      LOWER   => LOWER_BOUND_A,
      VAL_IN  => marko1_bc,
      VAL_OUT => marko1_xy,
      IN_TIME => hit_marko1
      );
  marko_2 : timewindow
    port map
    (
      CLK     => CLK ,
      UPPER   => UPPER_BOUND_A,
      LOWER   => LOWER_BOUND_A,
      VAL_IN  => marko2_bc,
      VAL_OUT => marko2_xy,
      IN_TIME => hit_marko2
      );

  william_1 : timewindow
    port map
    (
      CLK     => CLK ,
      UPPER   => UPPER_BOUND_A,
      LOWER   => LOWER_BOUND_A,
      VAL_IN  => william1_bc ,
      VAL_OUT => william1_xy ,
      IN_TIME => hit_william1
      );
  william_2 : timewindow
    port map
    (
      CLK     => CLK ,
      UPPER   => UPPER_BOUND_A,
      LOWER   => LOWER_BOUND_A,
      VAL_IN  => william2_bc ,
      VAL_OUT => william2_xy ,
      IN_TIME => hit_william2
      );

  harris_1 : timewindow
    port map
    (
      CLK     => CLK ,
      UPPER   => UPPER_BOUND_A,
      LOWER   => LOWER_BOUND_A,
      VAL_IN  => harris1_bc ,
      VAL_OUT => harris1_xy,
      IN_TIME => hit_harris1 
      );
  harris_2 : timewindow
    port map
    (
      CLK     => CLK ,
      UPPER   => UPPER_BOUND_A,
      LOWER   => LOWER_BOUND_A,
      VAL_IN  => harris2_bc ,
      VAL_OUT => harris2_xy,
      IN_TIME => hit_harris2 
      );

  helmut_1 : timewindow
    port map
    (
      CLK     => CLK ,
      UPPER   => UPPER_BOUND_A,
      LOWER   => LOWER_BOUND_A,
      VAL_IN  => helmut1_bc ,
      VAL_OUT => helmut1_xy,
      IN_TIME => hit_helmut1 
      );
  helmut_2 : timewindow
    port map
    (
      CLK     => CLK ,
      UPPER   => UPPER_BOUND_A,
      LOWER   => LOWER_BOUND_A,
      VAL_IN  => helmut2_bc ,
      VAL_OUT => helmut2_xy,
      IN_TIME => hit_helmut2 
      );

-------------------------------------------------------------------------------
-- output assignments
-------------------------------------------------------------------------------
  S_IRENA1_O   <= hit_irena1;
  S_EWA1_O     <= hit_ewa1;
  S_ANDREJ1_O  <= hit_andrej1;
  S_HEINZ1_O   <= hit_heinz1;
  S_MARKO1_O   <= hit_marko1;
  S_WILLIAM1_O <= hit_william1;
  S_HELMUT1_O  <= hit_helmut1;
  S_HARRIS1_O  <= hit_harris1;
  S_IRENA2_O   <= hit_irena2;
  S_EWA2_O     <= hit_ewa2;
  S_ANDREJ2_O  <= hit_andrej2;
  S_HEINZ2_O   <= hit_heinz2;
  S_MARKO2_O   <= hit_marko2;
  S_WILLIAM2_O <= hit_william2;
  S_HELMUT2_O  <= hit_helmut2;
  S_HARRIS2_O  <= hit_harris2;
  IRENA1_O     <= "00" & irena1_xy   when hit_irena1 = '1'   else (others => '0');
  EWA1_O       <= "00" & ewa1_xy     when hit_ewa1 = '1'     else (others => '0');
  ANDREJ1_O    <= "00" & andrej1_xy  when hit_andrej1 = '1'  else (others => '0');
  HEINZ1_O     <= "00" & heinz1_xy   when hit_heinz1 = '1'   else (others => '0');
  MARKO1_O     <= "00" & marko1_xy   when hit_marko1 = '1'   else (others => '0');
  WILLIAM1_O   <= "00" & william1_xy when hit_william1 = '1' else (others => '0');
  HARRIS1_O    <= "00" & harris1_xy  when hit_harris1 = '1'  else (others => '0');
  HELMUT1_O    <= "00" & helmut1_xy  when hit_helmut1 = '1'  else (others => '0');
  IRENA2_O     <= "00" & irena2_xy   when hit_irena2 = '1'   else (others => '0');
  EWA2_O       <= "00" & ewa2_xy     when hit_ewa2 = '1'     else (others => '0');
  ANDREJ2_O    <= "00" & andrej2_xy  when hit_andrej2 = '1'  else (others => '0');
  HEINZ2_O     <= "00" & heinz2_xy   when hit_heinz2 = '1'   else (others => '0');
  MARKO2_O     <= "00" & marko2_xy   when hit_marko2 = '1'   else (others => '0');
  WILLIAM2_O   <= "00" & william2_xy when hit_william2 = '1' else (others => '0');
  HARRIS2_O    <= "00" & harris2_xy  when hit_harris2 = '1'  else (others => '0');
  HELMUT2_O    <= "00" & helmut2_xy  when hit_helmut2 = '1'  else (others => '0');

end intime_arc;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:04 2008 for BCM-AAA by  1.5.7.1-20081012