cal.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/rio/cal.vhd,v $                                                  *
--*  $Revision: 1.6.2.5 $                                                *
--*  $Name: dev $                                                    *
--*  $Author: mniegl $                                                  *
--*  $Date: 2008/11/03 17:57:47 $                                                    *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;


entity cal is
  generic
    (
      ADJUST : integer := 0
      );
  port (
    CLK      : in  std_logic;
    STAT_R1  : in  std_logic;
    STAT_R2  : in  std_logic;
    STAT_R3  : in  std_logic;
    STAT_F1  : in  std_logic;
    STAT_F2  : in  std_logic;
    STAT_F3  : in  std_logic;
    RIS1     : in  std_logic_vector (5 downto 0);
    RIS2     : in  std_logic_vector (5 downto 0);
    RIS3     : in  std_logic_vector (5 downto 0);
    FAL1     : in  std_logic_vector (5 downto 0);
    FAL2     : in  std_logic_vector (5 downto 0);
    FAL3     : in  std_logic_vector (5 downto 0);
    S_T1     : out std_logic;
    S_T2     : out std_logic;
    S_T3     : out std_logic;
    S_W1     : out std_logic;
    S_W2     : out std_logic;
    S_W3     : out std_logic;
    TIME1    : out std_logic_vector (7 downto 0);
    TIME2    : out std_logic_vector (7 downto 0);
    TIME3    : out std_logic_vector (7 downto 0);
    WIDTH1   : out std_logic_vector (7 downto 0);
    WIDTH2   : out std_logic_vector (7 downto 0);
    WIDTH3   : out std_logic_vector (7 downto 0);
    SUM_RIN  : in  std_logic_vector (7 downto 0);
    SUM_FIN  : in  std_logic_vector (7 downto 0);
    SUM_ROUT : out std_logic_vector (7 downto 0);
    SUM_FOUT : out std_logic_vector (7 downto 0);
    OVER     : out std_logic
    );
end cal;


architecture cal_arc of cal is

-------------------------------- signals --------------------------------------
  signal time1_i  : std_logic_vector (5 downto 0) := (others => '0');
  signal time2_i  : std_logic_vector (5 downto 0) := (others => '0');
--  signal time3_i  : std_logic_vector (7 downto 0) := (others => '0');
  signal width1_i : std_logic_vector (7 downto 0) := (others => '0');
  signal width2_i : std_logic_vector (7 downto 0) := (others => '0');
--  signal width3_i : std_logic_vector (7 downto 0) := (others => '0');
  signal S_T1_i   : std_logic                     := '0';
  signal S_T2_i   : std_logic                     := '0';
--  signal S_T3_i   : std_logic                     := '0';
  signal S_W1_i   : std_logic                     := '0';
  signal S_W2_i   : std_logic                     := '0';
--  signal S_W3_i   : std_logic                     := '0';
  signal over_i   : std_logic                     := '0';

begin

  TIME1  <= "00" & time1_i;
  TIME2  <= "00" & time2_i;
  TIME3  <= (others => '0');            --time3_i;
  WIDTH1 <= width1_i;
  WIDTH2 <= width2_i;
  WIDTH3 <= (others => '0');            --width3_i;
  S_T1   <= S_T1_i;
  S_T2   <= S_T2_i;
  S_T3   <= '0';                        --S_T3_i;
  S_W1   <= S_W1_i;
  S_W2   <= S_W2_i;
  S_W3   <= '0';                        --S_W3_i;
  OVER   <= over_i;


  process (CLK)
  begin
    
    if CLK'event and CLK = '1' then
      
      SUM_ROUT <= SUM_RIN;
      SUM_FOUT <= SUM_FIN;

      over_i <= '0';

      if STAT_R1 = '1' then
        time1_i <= RIS1;
        S_T1_i  <= '1';
      else
        time1_i <= (others => '0');
        S_T1_i  <= '0';
      end if;
      if (STAT_F1 and STAT_R1) = '1' then
        if FAL1 < RIS1 then
          if RIS1 <= 32 then
            width1_i <= "00" & (32 - RIS1 + FAL1);
          else
            width1_i <= "00" & (64 - RIS1 + FAL1);
          end if;
        else
          width1_i <= "00" & FAL1 - RIS1;
        end if;
        S_W1_i <= '1';
      else
        if STAT_R1 = '1' then
          width1_i <= "00" & (64 - RIS1);
          S_W1_i   <= '1';
          over_i   <= '1';
        else
          width1_i <= (others => '0');
          S_W1_i   <= '0';
        end if;
      end if;

      if STAT_R2 = '1' then
        time2_i <= RIS2;
        S_T2_i  <= '1';
      else
        time2_i <= (others => '0');
        S_T2_i  <= '0';
      end if;
      if (STAT_F2 and STAT_R2) = '1' then
        if FAL2 < RIS2 then
          if RIS2 <= 32 then
            width2_i <= "00" & (32 - RIS2 + FAL2);
          else
            width2_i <= "00" & (64 - RIS2 + FAL2);
          end if;
        else
          width2_i <= "00" & FAL2 - RIS2;
        end if;
        S_W2_i <= '1';
      else
        if STAT_R2 = '1' then
          width2_i <= "00" & (64 - RIS2);
          S_W2_i   <= '1';
          over_i   <= '1';
        else
          width2_i <= (others => '0');
          S_W2_i   <= '0';
        end if;
      end if;

--      if STAT_R3 = '1' then
--        time3_i <= ("00" & RIS3);
--        S_T3_i  <= '1';
--      else
--        time3_i <= (others => '0');
--        S_T3_i  <= '0';
--      end if;
--      if STAT_F3 = '1' then
--        if FAL3 < RIS3 then
--          width3_i <= "00" & (32 - RIS3 + FAL3);
--        else
--          width3_i <= "00" & FAL3 - RIS3;
--        end if;
--        S_W3_i   <= '1';
--      else
--        if STAT_R3 = '1' then
--          width3_i <= "00" & (64 - RIS3);
--          S_W3_i   <= '1';
--          over_i   <= '1';
--        else
--          width3_i <= (others => '0');
--          S_W3_i   <= '0';
--        end if;
--      end if;
      
    end if;
  end process;
  
end cal_arc;

---

Author: M.Niegl

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