ddr_eth_buf.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/eth/ddr_eth_buf.vhd,v $                                                  *
--*  $Revision: 2.2.2.4 $                                                *
--*  $Name: dev $                                                    *
--*  $Author: mniegl $                                                  *
--*  $Date: 2008/11/03 17:57:46 $                                                    *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;

library unisim;

use unisim.vcomponents.all;



entity ddr_eth_buf is
  port (
    CLK_WR   : in  std_logic;
    CLK_RD   : in  std_logic;
    RES      : in  std_logic;
    RD       : in  std_logic;
    WR       : in  std_logic;
    DATA_IN  : in  std_logic_vector (63 downto 0);
    DATA_OUT : out std_logic_vector (7 downto 0)
    );
end ddr_eth_buf;



architecture ddr_eth_buf_arc of ddr_eth_buf is

  signal a_i : std_logic_vector(8 downto 0) := (others => '0');
  signal b_i : std_logic_vector(5 downto 0) := (others => '0');


  component ddreth_buf
    port (
      addra : in  std_logic_vector(8 downto 0);
      addrb : in  std_logic_vector(5 downto 0);
      clka  : in  std_logic;
      clkb  : in  std_logic;
      dinb  : in  std_logic_vector(63 downto 0);
      douta : out std_logic_vector(7 downto 0);
      ena   : in  std_logic;
      enb   : in  std_logic;
      web   : in  std_logic);
  end component;

begin


  wr_addr : process(CLK_WR)
  begin
    if CLK_WR'event and CLK_WR = '1' then
      if RES = '1' then
        b_i <= conv_std_logic_vector(24, 6);
      else
        if WR = '1' then
          if b_i = 47 then
            b_i <= (others => '0');
          else
            b_i <= b_i + 1;
          end if;
        else
          b_i <= b_i;
        end if;
      end if;
    end if;
  end process wr_addr;


  rd_addr : process(CLK_RD)
  begin
    if CLK_RD'event and CLK_RD = '1' then
      if RES = '1' then
        a_i <= (others => '0');
      else
        if RD = '1' then
          if a_i = 383 then
            a_i <= (others => '0');
          else
            a_i <= a_i + 1;
          end if;
        else
          a_i <= a_i;
        end if;
      end if;
    end if;
  end process rd_addr;


  bram_buf : ddreth_buf
    port map (
      addra => a_i ,
      addrb => b_i ,
      clka  => CLK_RD,
      clkb  => CLK_WR,
      dinb  => DATA_IN,
      douta => DATA_OUT,
      ena   => RD ,
      enb   => '1' ,
      web   => WR 
      );

end ddr_eth_buf_arc;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:04 2008 for BCM-AAA by  1.5.7.1-20081012