lvl1_buf.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/div/lvl1_buf.vhd,v $*
--*  $Revision: 1.31.2.3 $                                         *
--*  $Name: dev $                                             *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:45 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;

library unisim;

use unisim.vcomponents.all;







entity lvl1_buf is
  port (RESET      : in  std_logic;
        CLKWR      : in  std_logic;
        CLKRD      : in  std_logic;
        DATA_OUT   : out std_logic_vector (191 downto 0) := (others => '0');
        DATA_IN    : in  std_logic_vector (175 downto 0);
        WR_BID     : in  std_logic_vector (11 downto 0)  := "000000000000";
        RD_BID     : in  std_logic_vector (11 downto 0)  := "000000000000";
        VLD        : out std_logic;
        EN_B       : in  std_logic;
        NUM        : in  std_logic_vector(6 downto 0)    := "0000001";
        FINISH     : in  std_logic;
        all_READ   : out std_logic;
        PAUSE      : in  std_logic;
        READ_ERROR : out std_logic;
        WE         : in  std_logic
        );
end lvl1_buf;







architecture lvl1_buf_arc of lvl1_buf is
---------------------------- signals -------------------------------
  signal data_i      : std_logic_vector(191 downto 0) := (others => '0');
  signal data_out_i  : std_logic_vector(191 downto 0) := (others => '0');
  signal cnt_a       : std_logic_vector(11 downto 0)  := (others => '0');
  signal cnt_b       : std_logic_vector(11 downto 0)  := (others => '0');
  signal bid_lastin  : std_logic_vector(11 downto 0)  := (others => '0');
  signal bid_lastram : std_logic_vector(11 downto 0)  := (others => '0');
  signal num_i       : std_logic_vector(6 downto 0)   := "0000001";
  signal rden        : std_logic                      := '0';
  signal check       : std_logic                      := '0';
  signal rden_ram    : std_logic                      := '0';
  signal more        : std_logic                      := '0';
  signal more2       : std_logic                      := '0';
  signal allr        : std_logic                      := '0';
  signal nblock      : std_logic                      := '1';
  signal vld_i       : std_logic                      := '0';

---------------------------- components -------------------------------

  component lvl1_circ_buffer
    port (
      addra : in  std_logic_vector(11 downto 0);
      addrb : in  std_logic_vector(11 downto 0);
      clka  : in  std_logic;
      clkb  : in  std_logic;
      dina  : in  std_logic_vector(191 downto 0);
      doutb : out std_logic_vector(191 downto 0);
      ena   : in  std_logic;
      enb   : in  std_logic;
      wea   : in  std_logic);
  end component;

---------------------------- main code -------------------------------
begin

  READ_ERROR <= '0';
  all_READ   <= allr;
  VLD        <= vld_i;


  buf_i : lvl1_circ_buffer
    port map
    (
      addra => cnt_a,
      addrb => cnt_b,
      clka  => CLKWR,
      clkb  => CLKRD,
      dina  => data_i,
      doutb => data_out_i,
      ena   => '1' ,
      enb   => rden,
      wea   => WE 
      );


  addr_gen_a : process(CLKWR)
  begin
    if CLKWR'event and CLKWR = '1' then
      if RESET = '1' then
        cnt_a       <= (others => '0');
        data_i      <= (others => '0');
        bid_lastram <= (others => '0');
        bid_lastin  <= (others => '0');
      else
        if WE = '1' then
          cnt_a      <= WR_BID;         --* store last wr BID
          data_i     <= WR_BID & DATA_IN & "0000";
          bid_lastin <= WR_BID;
          if WR_BID = 0 then
            bid_lastram <= bid_lastin;
          else
            bid_lastram <= bid_lastram;
          end if;
        end if;
      end if;
    end if;
  end process addr_gen_a;


  rd_ram : process(CLKRD)
  begin
    if CLKRD'event and CLKRD = '1' then
      if RESET = '1' then
        cnt_b    <= (others => '0');
        rden_ram <= '0';
        more     <= '0';
      else
        if PAUSE = '0' then
          
          if EN_B = '1' then
            cnt_b    <= RD_BID;
            rden_ram <= '1';
            num_i    <= NUM;

            if NUM > 1 then
              more <= '1';
            else
              more <= '0';
            end if;
            
          elsif (more2 and nblock and (not rden_ram)) = '1' then
            rden_ram <= '1';
            num_i    <= num_i - 1;
            cnt_b    <= cnt_b + 1;
            if cnt_b = bid_lastram and bid_lastram > 0 then
              cnt_b <= (others => '0');
            end if;
            
          else
            cnt_b    <= cnt_b;
            rden_ram <= '0';
            more     <= '0';
          end if;
          
        else
          cnt_b    <= cnt_b;
          rden_ram <= '0';
        end if;
      end if;
    end if;
  end process;

  check <= rden when rising_edge(CLKRD);
  rden  <= rden_ram and nblock;


  fwd_data : process (CLKRD)
  begin  -- process fwd_data
    if CLKRD'event and CLKRD = '1' then  -- rising clock edge
      if RESET = '1' then
        allr     <= '0';
        vld_i    <= '0';
        DATA_OUT <= (others => '0');
      else
        if PAUSE = '0' then
          
          if check = '1' then
            DATA_OUT <= data_out_i;
            vld_i    <= '1';
            if more2 = '0' then
              allr <= '1';
            else
              allr <= '0';
            end if;
            
          else
            allr     <= '0';
            vld_i    <= '0';
            DATA_OUT <= (others => '0');
          end if;
          
        else
          allr     <= '0';
          vld_i    <= '0';
          DATA_OUT <= (others => '0');
        end if;
        
      end if;
    end if;
  end process fwd_data;


  latch_more2 : process (CLKRD, RESET)
  begin  -- process latch_more
    if RESET = '1' then                     -- asynchronous reset (active high)
      more2 <= '0';
    elsif CLKRD'event and CLKRD = '1' then  -- rising clock edge
      if (num_i-1) = 0 or FINISH = '1' then
        more2 <= '0';
      elsif more = '1' then
        more2 <= '1';
      end if;
    end if;
  end process latch_more2;


  latch_block : process (CLKRD, RESET)
  begin  -- process latch_more
    if RESET = '1' then                     -- asynchronous reset (active high)
      nblock <= '1';
    elsif CLKRD'event and CLKRD = '1' then  -- rising clock edge
      if vld_i = '1' then
        nblock <= '1';
      elsif rden = '1' then
        nblock <= '0';
      end if;
    end if;
  end process latch_block;
  
end lvl1_buf_arc;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:04 2008 for BCM-AAA by  1.5.7.1-20081012