busy.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/div/busy.vhd,v $
--*  $Revision: 1.5.2.3 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:45 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;



entity busy is
  generic (
    DEAD : integer range 0 to 30 := 10
    );
  port (
    CLK      : in  std_logic;
    RES      : in  std_logic;
    EN       : in  std_logic;
    TRIG_IN  : in  std_logic;
    TRIG_OUT : out std_logic
    );
end busy;



architecture busy_arc of busy is

  signal cnt    : std_logic_vector(4 downto 0) := (others => '0');
  signal trig_i : std_logic                    := '0';


  component edge
    port(
      CLK   : in  std_logic;
      A     : in  std_logic;
      PULSE : out std_logic
      );
  end component;

begin


  mask_trig : process(CLK)
  begin
    if CLK'event and CLK = '1' then
      if RES = '1' then
        cnt <= (others => '0');
      else
        if TRIG_IN = '1' then
          if cnt = DEAD-1 then
            trig_i <= '1';
            cnt    <= (others => '0');
          else
            cnt    <= cnt + 1;
            trig_i <= '0';
          end if;
        else
          cnt <= cnt;
        end if;
      end if;
    end if;
  end process mask_trig;


  make_edge : edge
    port map
    (
      CLK   => CLK ,
      A     => trig_i ,
      PULSE => TRIG_OUT
      );

end busy_arc;

---

Author: M.Niegl

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