extend_test.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/div/extend_test.vhd,v $
--*  $Revision: 1.7.2.3 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:45 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;





entity extend_test is
  generic (
    LEN : integer range 0 to 63 := 2
    );
  port (
    CLK  : in  std_logic;
    RES  : in  std_logic;
    ENDM : out std_logic;
    A    : in  std_logic;
    Y    : out std_logic
    );
end extend_test;



architecture extend_test_arc of extend_test is
  
  signal cn   : std_logic_vector(5 downto 0) := "000000";
  signal enab : std_logic                    := '0';
  
begin
  
  Y <= enab;


  extend : process(CLK)
  begin
    if(CLK'event and CLK = '1') then
      if RES = '1' then
        cn   <= (others => '0');
        ENDM <= '0';
      else
        ENDM <= '0';
        if enab = '1' then
          if cn = LEN then
            cn   <= (others => '0');
            enab <= '0';
            ENDM <= '1';
          else
            cn <= cn + 1;
          end if;
        else
          cn <= cn;
        end if;
        if A = '1' then
          enab <= '1';
        end if;
      end if;
    end if;
  end process extend;
  
end extend_test_arc;

---

Author: M.Niegl

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