00001 --**************************************************************
00002 --* *
00003 --* The source code for the ATLAS BCM "AAA" FPGA is made *
00004 --* available via the GNU General Public License (GPL) *
00005 --* unless otherwise stated below. *
00006 --* *
00007 --* In case of problems/questions/bug reports etc. please *
00008 --* contact michael.niegl@cern.ch *
00009 --* *
00010 --**************************************************************
00011
00012 --**************************************************************
00013 --* *
00014 --* $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr/mem_interface_top_data_path_0.vhd,v $ *
00015 --* $Revision: 1.2.2.3 $ *
00016 --* $Name: dev $ *
00017 --* $Author: mniegl $ *
00018 --* $Date: 2008/11/03 17:57:43 $ *
00019 --* *
00020 --**************************************************************
00021 -------------------------------------------------------------------------------
00022 -- Copyright (c) 2005 Xilinx, Inc.
00023 -- This design is confidential and proprietary of Xilinx, All Rights Reserved.
00024 -------------------------------------------------------------------------------
00025 -- ____ ____
00026 -- / /\/ /
00027 -- /___/ \ / Vendor: Xilinx
00028 -- \ \ \/ Version: 1.6
00029 -- \ \ Application : MIG
00030 -- / / Filename: mem_interface_top_data_path_0.vhd
00031 -- /___/ /\ Date Last Modified: Wed Jun 1 2005
00032 -- \ \ / \Date Created: Mon May 2 2005
00033 -- \___\/\___\
00034 -- Device: Virtex-4
00035 -- Design Name: DDR1_SDRAM
00036 -- Description: Instantiates the tap logic and the data write modules. Gives the
00037 -- rise and the fall data and the calibration information for the
00038 -- IDELAY elements.
00039 -------------------------------------------------------------------------------
00040
00041
00042 library ieee;
00043
00044 use ieee.std_logic_1164.all;
00045
00046 library unisim;
00047
00048 use unisim.vcomponents.all;
00049 use work.mem_interface_top_parameters_0.all;
00050
00051 entity mem_interface_top_data_path_0 is
00052 port(
00053 CLK : in ;
00054 CLK90 : in ;
00055 CAL_CLK : in ;
00056 RESET0 : in ;
00057 RESET90 : in ;
00058 RESET_CAL_CLK : in ;
00059 idelay_ctrl_rdy : in ;
00060 dummy_write_pattern : in ;
00061 CTRL_DUMMYREAD_START : in ;
00062 WDF_DATA : in ((data_width*2 -1) downto 0);
00063 MASK_DATA : in ((data_mask_width*2 -1) downto 0);
00064 CTRL_WREN : in ;
00065 CTRL_DQS_RST : in ;
00066 CTRL_DQS_EN : in ;
00067 dqs_delayed : in ((data_strobe_width -1) downto 0);
00068 data_idelay_inc : out ((ReadEnable - 1) downto 0);
00069 data_idelay_ce : out ((ReadEnable - 1) downto 0);
00070 data_idelay_rst : out ((ReadEnable - 1) downto 0);
00071 dqs_idelay_inc : out ((ReadEnable - 1) downto 0);
00072 dqs_idelay_ce : out ((ReadEnable - 1) downto 0);
00073 dqs_idelay_rst : out ((ReadEnable - 1) downto 0);
00074 SEL_DONE : out ;
00075 dqs_rst : out ;
00076 dqs_en : out ;
00077 wr_en : out ;
00078 wr_data_rise : out ((data_width -1) downto 0);
00079 wr_data_fall : out ((data_width -1) downto 0);
00080 mask_data_rise : out ((data_mask_width -1) downto 0);
00081 mask_data_fall : out ((data_mask_width -1) downto 0)
00082 );
00083 end mem_interface_top_data_path_0;
00084
00085 architecture arch of mem_interface_top_data_path_0 is
00086
00087 component mem_interface_top_data_write_0
00088 port( CLK : in ;
00089 CLK90 : in ;
00090 RESET0 : in ;
00091 RESET90 : in ;
00092 WDF_DATA : in ((data_width*2 -1) downto 0);
00093 MASK_DATA : in ((data_mask_width*2 -1) downto 0);
00094 dummy_write_pattern : in ;
00095 CTRL_WREN : in ;
00096 CTRL_DQS_RST : in ;
00097 CTRL_DQS_EN : in ;
00098 dqs_rst : out ;
00099 dqs_en : out ;
00100 wr_en : out ;
00101 wr_data_rise : out ((data_width -1) downto 0);
00102 wr_data_fall : out ((data_width -1) downto 0);
00103 mask_data_rise : out ((data_mask_width -1) downto 0);
00104 mask_data_fall : out ((data_mask_width -1) downto 0)
00105 );
00106 end component;
00107
00108 component mem_interface_top_tap_logic_0
00109 port( CLK : in ;
00110 CAL_CLK : in ;
00111 RESET0 : in ;
00112 RESET_CAL_CLK : in ;
00113 idelay_ctrl_rdy : in ;
00114 CTRL_DUMMYREAD_START : in ;
00115 dqs_delayed : in ((data_strobe_width -1) downto 0);
00116 data_idelay_inc : out ((ReadEnable - 1) downto 0);
00117 data_idelay_ce : out ((ReadEnable - 1) downto 0);
00118 data_idelay_rst : out ((ReadEnable - 1) downto 0);
00119 dqs_idelay_inc : out ((ReadEnable - 1) downto 0);
00120 dqs_idelay_ce : out ((ReadEnable - 1) downto 0);
00121 dqs_idelay_rst : out ((ReadEnable - 1) downto 0);
00122 SEL_DONE : out
00123 );
00124 end component;
00125
00126 begin
00127
00128 data_write_10: mem_interface_top_data_write_0 port map
00129 ( CLK => CLK,
00130 CLK90 => CLK90,
00131 RESET0 => RESET0,
00132 RESET90 => RESET90,
00133 WDF_DATA => WDF_DATA,
00134 MASK_DATA => MASK_DATA,
00135 dummy_write_pattern => dummy_write_pattern,
00136 CTRL_WREN => CTRL_WREN,
00137 CTRL_DQS_RST => CTRL_DQS_RST,
00138 CTRL_DQS_EN => CTRL_DQS_EN,
00139 dqs_rst => dqs_rst,
00140 dqs_en => dqs_en,
00141 wr_en => wr_en,
00142 wr_data_rise => wr_data_rise,
00143 wr_data_fall => wr_data_fall,
00144 mask_data_rise => mask_data_rise,
00145 mask_data_fall => mask_data_fall
00146 );
00147
00148 tap_logic_00: mem_interface_top_tap_logic_0 port map
00149 ( CLK => CLK,
00150 CAL_CLK => CAL_CLK,
00151 RESET0 => RESET0,
00152 RESET_CAL_CLK => RESET_CAL_CLK,
00153 idelay_ctrl_rdy => idelay_ctrl_rdy,
00154 CTRL_DUMMYREAD_START => CTRL_DUMMYREAD_START,
00155 dqs_delayed => dqs_delayed,
00156 data_idelay_inc => data_idelay_inc,
00157 data_idelay_ce => data_idelay_ce,
00158 data_idelay_rst => data_idelay_rst,
00159 dqs_idelay_inc => dqs_idelay_inc,
00160 dqs_idelay_ce => dqs_idelay_ce,
00161 dqs_idelay_rst => dqs_idelay_rst,
00162 SEL_DONE => SEL_DONE
00163 );
00164
00165 end arch;