ddr2_mem_idelay_ctrl.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr2/ddr2_mem_idelay_ctrl.vhd,v $
--*  $Revision: 1.2.2.4 $                                      *
--*  $Name: dev $                                              *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:44 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;
-- pragma translate_off

library unisim;

use unisim.vcomponents.all;
-- pragma translate_on






entity ddr2_mem_idelay_ctrl is
  port (
    CLK200     : in  std_logic;
    RESET      : in  std_logic;
    RDY_STATUS : out std_logic
    );

end entity;


architecture arc_idelay_ctrl of ddr2_mem_idelay_ctrl is


  component IDELAYCTRL
    port(
      RDY    : out std_ulogic;
      REFCLK : in  std_ulogic;
      RST    : in  std_ulogic
      );
  end component;

begin


  idelayctrl0 : IDELAYCTRL
    port map (
      RDY     => RDY_STATUS ,
      REFCLK  => CLK200,
      RST     => RESET
      );

end arc_idelay_ctrl;

---

Author: M.Niegl

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