- b -

• B : comparator4 , delay_adj , onescomplementadder
• B_DATA_CONTROL_IN : sata
• B_DATA_CONTROL_OUT : sata
• B_DATA_ERROR : bridge
• B_DATA_ERROR_OUT : sata
• B_DATA_IN : bridge , sata
• B_DATA_OUT : bridge , sata
• B_DATA_READY_IN : sata
• B_DATA_READY_OUT : sata
• B_DATA_VALID_IN : bridge
• B_DATA_VALID_OUT : bridge
• B_EOP_IN : sata
• B_EOP_OUT : sata
• B_LISTENING : bridge
• B_PACKAGE_BAD : bridge
• B_PACKAGE_GOOD : bridge
• B_PACKAGE_OK_OUT : sata
• backend_fifos_00 : ddr2_mem_user_interface_0.user_interface_arc
• badcnt : auto_receiver
• BC : BID_cnt , daqrio_top
• BC_2X : rio_rxtx
• BCID : abort_controller , ltp_comm , tdaq_collector
• BCID_R : abort_controller
• BCLK : ltp_comm , rio2mem , rios_all , side_4rios , clocks
• BCLK2X : rios_all , side_4rios
• BCLK2X_N : clocks , rio2mem
• BCLK2X_P : clocks , rio2mem
• BCLK2X_P_BUF : clocks.coldplay
• BCLK4X : clocks , rios_all , side_4rios
• BCLK4X_N : clocks , rio2mem
• BCLK4X_P : clocks , rio2mem
• BCLK_BUF : clocks.coldplay
• bcm_emac_fifo : temac_controller.temac_controller_arc
• bcm_emac_fifo_rx : temac_controller.temac_controller_arc
• bcm_rod : main_components
• bcm_rod_dp_ram : bcm_rod_ram.bcm_rod_ram_arc
• bcm_rod_dp_updown_counter : bcm_rod_ram.bcm_rod_ram_arc
• bcm_rod_formatter : bcm_rod.bcm_rod_arc
• bcm_rod_formatter_fsm_state_typedef : bcm_rod_formatter.bcm_rod_formatter_arc
• bcm_rod_ram : bcm_rod.bcm_rod_arc
• bcm_rod_slink : bcm_rod_formatter.bcm_rod_formatter_arc
• bcm_rod_treadmil : bcm_rod.bcm_rod_arc
• bcm_signal_delay : main_components
• bcm_signal_delay_vec : main_components , daqrio_top.daqrio_top_arc
• bcm_slink_fsm_state_typedef : bcm_rod_slink.bcm_rod_slink_arc
• BCR : bcm_aaa , BID_cnt , ltp_comm , rio2mem
• BEAM_PERM : tdaq_collector
• BEAM_PERM_1 : bcm_aaa , rio2mem , cibu_comm
• BEAM_PERM_2 : bcm_aaa , cibu_comm , rio2mem
• BEAM_PERM_SET : cibu_comm
• BEAM_PERM_SET_EN : cibu_comm
• BEAM_PERMIT : command_decoder
• BID : BID_cnt
• BID_cnt : ltp_comm.ltp_comm_arc , main_components
• BOARD : rio_rxtx
• bram_buf : ddr_eth_buf.ddr_eth_buf_arc , ddr_data_buffer.ddr_data_buffer_arc
• bridge : main_components
• buf_i : lvl1_buf.lvl1_buf_arc , abort_controller.abort_controller_arc
• BUFFER_DUMP_START : command_decoder
• BUFFER_DUMP_STOP : command_decoder
• BUFG : ddr2_mem_infrastructure.arc_infrastructure , ram_user_backend.ram_user_backend_arc , mem_interface_top_infrastructure.arch
• build_parameters : udp_addresses , bcm_aaa , status_collector
• bunch_counter : rio2mem.rio2mem_arc , ltp_comm.ltp_comm_arc
• bunchcycle : daqrio_top.daqrio_top_arc
• bunchcycle_e : daqrio_top.daqrio_top_arc
• bunchcycle_i : daqrio_top.daqrio_top_arc
• BURST_LENGTH : ddr2_mem_top_0
• burst_length : ddr2_mem_ddr2_controller_0
• busy : bcm_rod_dp_updown_counter , bcm_rod_ram , bcm_rod_treadmil
• BUSY : lcd_commander , lcd_controller
• busy : auto_receiver
• BUSY : tdaq_collector
• busy : main_components
• BUSY : bcm_aaa , rio2mem
• BUSY_EXT : tdaq_collector
• busy_extend : rio2mem.rio2mem_arc
• BUSY_EXTERNAL : command_decoder
• BUSY_EXTERNAL_CLR : command_decoder
• BYTE_IN : ethernet_top