a_i (defined in eth_buf.eth_buf_arc) | eth_buf.eth_buf_arc | [Signal] |
b_i (defined in eth_buf.eth_buf_arc) | eth_buf.eth_buf_arc | [Signal] |
bram_buf (defined in eth_buf.eth_buf_arc) | eth_buf.eth_buf_arc | [Component Instantiation] |
CLK_RD | eth_buf | [Port] |
CLK_WR | eth_buf | [Port] |
DATA_IN | eth_buf | [Port] |
DATA_OUT | eth_buf | [Port] |
ethbuf | eth_buf.eth_buf_arc | [Component] |
ieee | eth_buf | [Library] |
numeric_std | eth_buf | [Package] |
RD | eth_buf | [Port] |
rd_addr(CLK_RD) | eth_buf.eth_buf_arc | [Process] |
RES | eth_buf | [Port] |
std_logic_1164 | eth_buf | [Package] |
std_logic_arith | eth_buf | [Package] |
std_logic_unsigned | eth_buf | [Package] |
unisim | eth_buf | [Library] |
vcomponents | eth_buf | [Package] |
WR | eth_buf | [Port] |
wr_addr(CLK_WR) | eth_buf.eth_buf_arc | [Process] |