ddr2_mem_tap_ctrl Member List

This is the complete list of members for ddr2_mem_tap_ctrl, including all inherited members.

CAL_CLK (defined in ddr2_mem_tap_ctrl)	ddr2_mem_tap_ctrl	[Port]
CTRL_DUMMYREAD_START (defined in ddr2_mem_tap_ctrl)	ddr2_mem_tap_ctrl	[Port]
curr_dqs_level (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
data_bit_tap_count (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
data_count_valid (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
DATA_TAP_COUNT (defined in ddr2_mem_tap_ctrl)	ddr2_mem_tap_ctrl	[Port]
delay_sel_done (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
detect_edge	ddr2_mem_tap_ctrl.arch	[Constant]
detect_edge_idle (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
detect_edge_idle_r1 (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
detect_edge_idle_r2 (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
detect_edge_idle_r3 (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
detect_edge_idle_r4 (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
detect_edge_idle_r5 (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
detect_edge_idle_r6 (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
dly_after_first (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
dly_after_first_cnt (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
dly_ce (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
dly_inc (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
dly_rst (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
DLYCE (defined in ddr2_mem_tap_ctrl)	ddr2_mem_tap_ctrl	[Port]
DLYINC (defined in ddr2_mem_tap_ctrl)	ddr2_mem_tap_ctrl	[Port]
DLYRST (defined in ddr2_mem_tap_ctrl)	ddr2_mem_tap_ctrl	[Port]
DQS (defined in ddr2_mem_tap_ctrl)	ddr2_mem_tap_ctrl	[Port]
first_edge (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
first_edge_cnt (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
first_edge_tap_count (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
flag (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
idelay_inc	ddr2_mem_tap_ctrl.arch	[Constant]
idelay_inc_idle (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
idelay_inc_idle_r1 (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
idelay_inc_idle_r2 (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
idelay_inc_idle_r3 (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
idelay_inc_idle_r4 (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
idelay_inc_idle_r5 (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
idelay_inc_idle_r6 (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
idelay_rst	ddr2_mem_tap_ctrl.arch	[Constant]
idelay_rst_idle (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
idelay_rst_idle_r1 (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
idelay_rst_idle_r2 (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
idelay_rst_idle_r3 (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
idelay_rst_idle_r4 (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
idelay_rst_idle_r5 (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
idelay_rst_idle_r6 (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
idle	ddr2_mem_tap_ctrl.arch	[Constant]
ieee	ddr2_mem_tap_ctrl	[Library]
prev_dqs_level (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
PROCESS_149(CAL_CLK)	ddr2_mem_tap_ctrl.arch	[Process]
PROCESS_150(CAL_CLK)	ddr2_mem_tap_ctrl.arch	[Process]
PROCESS_151(CAL_CLK)	ddr2_mem_tap_ctrl.arch	[Process]
PROCESS_152(CAL_CLK)	ddr2_mem_tap_ctrl.arch	[Process]
PROCESS_153(CAL_CLK)	ddr2_mem_tap_ctrl.arch	[Process]
PROCESS_154(CAL_CLK)	ddr2_mem_tap_ctrl.arch	[Process]
PROCESS_155(CAL_CLK)	ddr2_mem_tap_ctrl.arch	[Process]
PROCESS_156(CAL_CLK)	ddr2_mem_tap_ctrl.arch	[Process]
PROCESS_157(CAL_CLK)	ddr2_mem_tap_ctrl.arch	[Process]
PROCESS_158(CAL_CLK)	ddr2_mem_tap_ctrl.arch	[Process]
PROCESS_159(CAL_CLK)	ddr2_mem_tap_ctrl.arch	[Process]
PROCESS_160(CAL_CLK)	ddr2_mem_tap_ctrl.arch	[Process]
PROCESS_161(CAL_CLK)	ddr2_mem_tap_ctrl.arch	[Process]
pulse_center_tap_count (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
pulse_width_tap_count (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
RDY_STATUS (defined in ddr2_mem_tap_ctrl)	ddr2_mem_tap_ctrl	[Port]
RESET (defined in ddr2_mem_tap_ctrl)	ddr2_mem_tap_ctrl	[Port]
reset_int (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
second_edge (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
second_edge_r1 (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
second_edge_r2 (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
second_edge_r3 (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
second_edge_tap_count (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
sel_complete (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
SEL_DONE (defined in ddr2_mem_tap_ctrl)	ddr2_mem_tap_ctrl	[Port]
state (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
std_logic_1164	ddr2_mem_tap_ctrl	[Package]
std_logic_unsigned	ddr2_mem_tap_ctrl	[Package]
tap_counter (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
transition (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
transition_rst (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
unisim	ddr2_mem_tap_ctrl	[Library]
valid_data_count (defined in ddr2_mem_tap_ctrl.arch)	ddr2_mem_tap_ctrl.arch	[Signal]
VALID_DATA_TAP_COUNT (defined in ddr2_mem_tap_ctrl)	ddr2_mem_tap_ctrl	[Port]
vcomponents	ddr2_mem_tap_ctrl	[Package]