, including all inherited members.
| ACT (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ACT_r (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ACTIVE (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| ACTIVE_WAIT (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| ADDITIVE_LATENCY_VALUE (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| af_addr | ddr2_mem_ddr2_controller_0 | [Port] |
| af_addr_r (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| af_addr_r1 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| af_empty | ddr2_mem_ddr2_controller_0 | [Port] |
| af_empty_r (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| af_rden (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| auto_cnt (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| auto_ref (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| AUTO_REFRESH (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| AUTO_REFRESH_WAIT (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| burst_cnt (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| burst_length | ddr2_mem_ddr2_controller_0 | [Port] |
| BURST_LENGTH_VALUE (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| BURST_READ (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| BURST_WRITE (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| cas_check_count (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| cas_count (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| CAS_LATENCY_VALUE (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| chip_cnt (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| cke_200us_cnt (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| clk0 | ddr2_mem_ddr2_controller_0 | [Port] |
| cntnext (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| command_address (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| COMP_DONE | ddr2_mem_ddr2_controller_0 | [Port] |
| COMP_DONE_r (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| conflict_detect (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| conflict_detect_r (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| conflict_resolved_r (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| count6 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| count_200_cycle (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| count_200cycle_done_r (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| cs_width0 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| cs_width1 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_af_RdEn | ddr2_mem_ddr2_controller_0 | [Port] |
| ctrl_ddr2_address | ddr2_mem_ddr2_controller_0 | [Port] |
| ctrl_ddr2_ba | ddr2_mem_ddr2_controller_0 | [Port] |
| ctrl_ddr2_cas_L | ddr2_mem_ddr2_controller_0 | [Port] |
| ctrl_ddr2_cke | ddr2_mem_ddr2_controller_0 | [Port] |
| ctrl_ddr2_cs_L | ddr2_mem_ddr2_controller_0 | [Port] |
| ctrl_ddr2_odt | ddr2_mem_ddr2_controller_0 | [Port] |
| ctrl_ddr2_ras_L | ddr2_mem_ddr2_controller_0 | [Port] |
| ctrl_ddr2_we_L | ddr2_mem_ddr2_controller_0 | [Port] |
| ctrl_Dqs_En | ddr2_mem_ddr2_controller_0 | [Port] |
| ctrl_Dqs_En_r1 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_Dqs_Rst | ddr2_mem_ddr2_controller_0 | [Port] |
| ctrl_Dqs_Rst_r1 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_dummy_wr_sel | ddr2_mem_ddr2_controller_0 | [Port] |
| ctrl_dummy_write (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_Dummyread_Start | ddr2_mem_ddr2_controller_0 | [Port] |
| ctrl_Dummyread_Start_r1 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_Dummyread_Start_r2 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_Dummyread_Start_r3 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_Dummyread_Start_r4 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_init_done (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_odt (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_RdEn | ddr2_mem_ddr2_controller_0 | [Port] |
| ctrl_RdEn_r1 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_read_en (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_read_en_r (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_read_en_r1 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_read_en_r2 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_read_en_r3 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_Wdf_RdEn | ddr2_mem_ddr2_controller_0 | [Port] |
| ctrl_Wdf_RdEn_int (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_wdf_read_en (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_wdf_read_en_r1 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_wdf_read_en_r2 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_wdf_read_en_r3 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_wdf_read_en_r4 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_wdf_read_en_r5 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_wdf_read_en_r6 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_WrEn | ddr2_mem_ddr2_controller_0 | [Port] |
| ctrl_WrEn_cnt (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_WrEn_r1 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_write_en (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_write_en_r1 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_write_en_r2 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_write_en_r3 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_write_en_r4 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_write_en_r5 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ctrl_write_en_r6 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ddr2_address_init_r (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ddr2_address_r1 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ddr2_address_r2 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ddr2_ba_r1 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ddr2_ba_r2 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ddr2_cas_r (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ddr2_cas_r2 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ddr2_cas_r3 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ddr2_cke_r (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ddr2_cs_r (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ddr2_cs_r1 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ddr2_cs_r_odt (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ddr2_cs_r_out (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ddr2_mem_parameters_0 (defined in ddr2_mem_ddr2_controller_0) | ddr2_mem_ddr2_controller_0 | [Package] |
| ddr2_ras_r (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ddr2_ras_r2 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ddr2_ras_r3 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ddr2_we_r (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ddr2_we_r2 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ddr2_we_r3 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| done_200us (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| dqs_en (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| dqs_en_r1 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| dqs_en_r2 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| dqs_en_r3 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| dqs_en_r4 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| dqs_en_r5 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| dqs_en_r6 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| dqs_reset (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| dqs_reset_r1 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| dqs_reset_r2 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| dqs_reset_r3 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| dqs_reset_r4 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| dqs_reset_r5 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| dqs_reset_r6 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| dummy_read_en (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| dummy_write_flag | ddr2_mem_ddr2_controller_0 | [Port] |
| dummy_write_flag_r (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| dummy_write_state (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| dummy_write_state_r (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ECC_VALUE (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| equivalent_register_removal (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Attribute] |
| equivalent_register_removal (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Attribute] |
| ext_mode_reg (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| FIRST_READ (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| FIRST_WRITE (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| IDLE (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| idle_cnt (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ieee | ddr2_mem_ddr2_controller_0 | [Library] |
| INIT_ACTIVE (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| INIT_ACTIVE_WAIT (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| INIT_AUTO_REFRESH (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| INIT_AUTO_REFRESH_WAIT (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| init_count (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| INIT_COUNT_200 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| INIT_COUNT_200_WAIT (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| init_count_cp (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| INIT_DEEP_MEMORY_ST (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| init_done (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| INIT_DUMMY_ACTIVE (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| INIT_DUMMY_ACTIVE_WAIT (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| INIT_DUMMY_FIRST_READ (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| INIT_DUMMY_READ (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| INIT_DUMMY_READ_CYCLES (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| INIT_DUMMY_READ_WAIT (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| INIT_IDLE (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| INIT_LOAD_MODE (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| init_memory (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| INIT_MODE_REGISTER_WAIT (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| init_next_state (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| INIT_PATTERN_READ (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| INIT_PATTERN_READ_WAIT (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| INIT_PATTERN_WRITE (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| INIT_PATTERN_WRITE_READ (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| INIT_PRECHARGE (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| INIT_PRECHARGE_WAIT (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| init_state (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| init_state_r2 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| LMR (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| LMR_PRE_REF_ACT_cmd_r (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| LMR_r (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| LOAD_MODE (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| load_mode_reg (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| MODE_REGISTER_WAIT (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| mrd_count (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| next_state (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| numeric_std | ddr2_mem_ddr2_controller_0 | [Package] |
| odt_cnt (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| odt_en (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| odt_en_cnt (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ODT_ENABLE (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| phy_Dly_Slct_Done | ddr2_mem_ddr2_controller_0 | [Port] |
| PRE (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| pre_cnt (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| PRE_r (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| PRECHARGE (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| PRECHARGE_WAIT (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| PROCESS_100(RD, RD_r, WR, WR_r, LMR_r, PRE_r, ACT_r, REF_r,auto_ref, chip_cnt, auto_cnt, conflict_detect, conflict_detect_r,conflict_resolved_r, count_200cycle_done_r, idle_cnt,init_count, init_memory, mrd_count, LMR_PRE_REF_ACT_cmd_r,phy_Dly_Slct_Done, ras_count, rcd_count, rd_to_wr_count,read_burst_cnt, rfc_count, rp_count, rtp_count, pre_cnt,state, wr_to_rd_count, wrburst_cnt, wtp_count, done_200us,cs_width1, dummy_write_flag_r, COMP_DONE_r, init_done, af_empty_r) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_101(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_102(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_103(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_104(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_105(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_106(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_107(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_108(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_109(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_110(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_111(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_112(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_113(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_114(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_115(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_116(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_117(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_118(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_119(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_120(rst, odt_en_cnt, odt_cnt) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_121(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_40(clk0) (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_41(clk0) (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_42(command_address, ctrl_init_done, af_empty) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_43(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_44(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_45(clk0) (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_46(clk0) (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_47(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_48(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_49(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_50(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_51(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_52(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_53(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_54(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_55(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_56(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_57(refresh_clk) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_58(refi_count, done_200us) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_59(refresh_clk) (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_60(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_61(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_62(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_63(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_64(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_65(BURST_LENGTH_VALUE) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_66(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_67(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_68(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_69(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_70(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_71(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_72(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_73(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_74(ctrl_WrEn_cnt) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_75(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_76(state, init_state) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_77(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_78(state, init_state, wrburst_cnt) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_79(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_80(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_81(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_82(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_83(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_84(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_85(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_86(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_87(rdburst_cnt) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_88(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_89(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_90(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_91(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_92(burst_cnt, wdf_rden_r, wdf_rden_r2, wdf_rden_r3, wdf_rden_r4) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_93(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_94(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_95(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_96(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_97(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_98(clk0) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| PROCESS_99(RD, RD_r, WR, WR_r, LMR_r, PRE_r, ACT_r, REF_r,auto_ref, chip_cnt, auto_cnt, conflict_detect, conflict_detect_r,conflict_resolved_r, count_200cycle_done_r, idle_cnt,init_count, init_memory, mrd_count, LMR_PRE_REF_ACT_cmd_r,phy_Dly_Slct_Done, ras_count, rcd_count, rd_to_wr_count,read_burst_cnt, rfc_count, rp_count, rtp_count,init_state, wr_to_rd_count, wrburst_cnt, wtp_count, done_200us,cs_width0, dummy_write_flag_r, COMP_DONE_r, count6) | ddr2_mem_ddr2_controller_0.arc_controller | [Process] |
| ras_count (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| rcd_count (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| RD (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| RD_r (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| rd_to_wr_count (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| rdburst_cnt (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| read_burst_cnt (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| READ_WAIT (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| READ_WRITE (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| REF (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ref_flag (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ref_flag_266 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| ref_flag_266_r (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| REF_r (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| refi_count (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| refresh_clk | ddr2_mem_ddr2_controller_0 | [Port] |
| REGISTERED_VALUE (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| rfc_count (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| row_addr_r (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| rp_count (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| rst | ddr2_mem_ddr2_controller_0 | [Port] |
| rtp_count (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| s1_h (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| s2_h (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| s3_h (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| s4_h (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| s5_h (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| state (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| state_r2 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| state_r3 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| std_logic_1164 | ddr2_mem_ddr2_controller_0 | [Package] |
| std_logic_unsigned | ddr2_mem_ddr2_controller_0 | [Package] |
| unisim | ddr2_mem_ddr2_controller_0 | [Library] |
| vcomponents | ddr2_mem_ddr2_controller_0 | [Package] |
| wdf_rden_r (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| wdf_rden_r2 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| wdf_rden_r3 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| wdf_rden_r4 (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| work (defined in ddr2_mem_ddr2_controller_0) | ddr2_mem_ddr2_controller_0 | [Library] |
| WR (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| WR_r (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| wr_to_rd_count (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| wrburst_cnt (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
| WRITE_READ (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| WRITE_WAIT (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Constant] |
| wtp_count (defined in ddr2_mem_ddr2_controller_0.arc_controller) | ddr2_mem_ddr2_controller_0.arc_controller | [Signal] |
1.5.7.1-20081012