A (defined in edge_fal) | edge_fal | [Port] |
CLK (defined in edge_fal) | edge_fal | [Port] |
ieee | edge_fal | [Library] |
latch1 (defined in edge_fal.edge_fal_arc) | edge_fal.edge_fal_arc | [Signal] |
latch2 (defined in edge_fal.edge_fal_arc) | edge_fal.edge_fal_arc | [Signal] |
latches(CLK) (defined in edge_fal.edge_fal_arc) | edge_fal.edge_fal_arc | [Process] |
PULSE (defined in edge_fal) | edge_fal | [Port] |
std_logic_1164 | edge_fal | [Package] |
std_logic_arith | edge_fal | [Package] |
std_logic_unsigned | edge_fal | [Package] |