a_i (defined in ddr_eth_buf.ddr_eth_buf_arc) | ddr_eth_buf.ddr_eth_buf_arc | [Signal] |
b_i (defined in ddr_eth_buf.ddr_eth_buf_arc) | ddr_eth_buf.ddr_eth_buf_arc | [Signal] |
bram_buf | ddr_eth_buf.ddr_eth_buf_arc | [Component Instantiation] |
CLK_RD | ddr_eth_buf | [Port] |
CLK_WR | ddr_eth_buf | [Port] |
DATA_IN | ddr_eth_buf | [Port] |
DATA_OUT | ddr_eth_buf | [Port] |
ddreth_buf | ddr_eth_buf.ddr_eth_buf_arc | [Component] |
ieee | ddr_eth_buf | [Library] |
numeric_std | ddr_eth_buf | [Package] |
RD | ddr_eth_buf | [Port] |
rd_addr(CLK_RD) | ddr_eth_buf.ddr_eth_buf_arc | [Process] |
RES | ddr_eth_buf | [Port] |
std_logic_1164 | ddr_eth_buf | [Package] |
std_logic_arith | ddr_eth_buf | [Package] |
std_logic_unsigned | ddr_eth_buf | [Package] |
unisim | ddr_eth_buf | [Library] |
vcomponents | ddr_eth_buf | [Package] |
WR | ddr_eth_buf | [Port] |
wr_addr(CLK_WR) | ddr_eth_buf.ddr_eth_buf_arc | [Process] |